lFirst Xtensa implementation with traditional RISC five
stage pipeline.
lProcessor accesses instruction cache and tags in first
half of I stage. Computes cache hit/miss signal in 2nd half.
lInstruction
is decoded and register file is accessed in R stage.
lMachine computes
effective address for loads and stores and executes ALU instructions on E stage and also determines
if conditional branch is taken.
lFor loads, the processor accesses data cache in the
first half o the M stage and computes the
cache hit/miss signal in 2nd half.
lRegister file is updated in W stage.
l