nVerilog
•In November 1999, Open Verilog International announced its
plans for an SLD
•Efforts were however hw focused; it was
announced that the main goal was to enhance the productivity of the Verilog
HDL user
nVSPEC
•Developed at University of Cincinnati & funded by Arpa RASSP
contract
•VSEC is a VHDL-based interface language that
can represent both hw and sw as formal properties and constraints by
adding annotation to VHDL entries