1/23/2002
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System Level Architecture Exploration Process
­Five target architecture models are explored:
­Pure_SW model:  four leaf nodes are implemented in the SW.
­SW_HW sequential model: a HW is used to run DCT block while other leaf nodes remain in SW. ­SW_HW parallel model: SW and HW are scheduled to run different 8*8 pixel blocks input concurrently. ­SW_2HW parallel model: two HW and one SW are used to run different 8*8 pixel blocks input concurrently. ­SW_2HW shared memory  parallel model: a global memory is used to implement shared memory communication,instead of message passing communication.