UCR CS269: Hardware/Software Engineering of Embedded Systems

Course Information   Class Readings and Presentations   Individual Projects  

CS269 deals with the exciting and rapidly-growing field of embedded computing systems.  The course will present state-of-the-art software and hardware design techniques for embedded computing systems.  Topics include specification models, languages, simulation, partitioning algorithms, estimation methods, model refinement, and design methodology.  This year we will have a slight focus on the specification model, design methodology, and formal methods.

Course information

Instructor Harry Hsieh, (harry@cs.ucr.edu), SURGE 329

Office hours: Tue/Thu 2-3PM, or by appointment

Class meeting Surge 349, TR 12:40PM-2PM
Textbooks None -- all readings will be available online
Prerequisite CS/EE120A(Digital systems) and consent of instructor
Call # and units 16546, 4 units.
Grade Individual Project 45%, Class Presentation & Participation  45%, Quizzes 10%

Project may be done in a team of 1 or 2.  A list of proposed projects will be available at the beginning of the class.  You may also propose your own project, as long as the topic falls within the confine of the course and it has comparable depth as the other projects.

You are expected to read assigned readings before the date they are presented, to attend classes and actively participate in discussions.  You are also expected to present several papers during the quarter, for which you should study thoroughly, and do outside research as necessary.  

There will be open-book quizzes during the quarter on topics taken from the assigned papers and presentations.  

 

Class Readings and Presentation

You are expected to read assigned readings before the date they are presented, to attend classes and actively participate in discussions.  You are also expected to present several papers during the quarter, for which you should study thoroughly, and do outside research as necessary.  For the presenter, the papers listed under "Extra reading" is strongly recommended.

Deadlines:  You must choose the papers for the first round of presentation by noon Thursday 1/10.  The deadline for choosing the second round of papers will be announced later

Date Presenter Topic and assigned reading Extra reading, references, and links Presentation
Tu 1/8 H. Hsieh Course Introduction and Class Logistics

Int. Technology Roadmap for Semiconductors: Executive Summary

ITRS'01: System Drivers

ITRS'01: Design

public.itrs.net HTML

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Th 1/10 H. Hsieh F. Balarin et. al., "Metropolis: Design Environment for Heterogeneous Systems", Cadence Technical Conference 2001 (internal documentation)

F. Balarin et. al., "Modeling and Designing Heterogeneous Systems", (to appear)

F. Balarin et. al., "Constraints Specification at Higher Levels of Abstraction", International High-Level Design Validation and Test Workshop, Nov 2001.

gigascale.org/metropolis

"The metropolis Meta-Model, version 0.2.7", Metropolis project Team. (unpublished, internal documentation, a little dated)

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Tu 1/15 X. Chen Ptolemy II presentations:

E. Lee, "Computing for Embedded Systems", IMTC01

E. Lee, "Overview of the Ptolemy Project", UCB Technical Memo UCB/ERL M01/11.

ptolemy.eecs.berkeley.edu/ptolemyII

E. Lee et. al. "Synchronous Data Flow", Proc. of the IEEE, September, 1987.

J. Buck et. al., Ptolemy: "A Framework for Simulating and Prototyping Heterogeneous Systems", Int. Journal of Computer Simulation, special issue on "Simulation Software Development," vol. 4, pp. 155-182, April, 1994

E. Lee et. al., "Dataflow Process Networks", Proceedings of the IEEE, vol. 83, no. 5, pp 773-801, May, 1995

S. Bhattacharyya et. al., "Looped Schedules for Dataflow Descriptions of Multirate Signal Processing Algorithms", Formal Methods in System Design, December 1994.

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H. Hsieh Metropolis (continue) HTML

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Thu 1/17 F. Chen Spin and formal verification presentations:

"Basic Spin Manual"

netlib.bell-labs.com/netlib/spin/whatispin.html

"What's new in Spin version 2.0 and 3.0"

T. Ball et. al., "Automatically validating temporal safety properties of interfaces", SPIN workshop, May 2001.

R. Gerth, "Modeling checking if your life depends on it: a view from Intel's trenches", Spin workshop, May 2001, (presentation)

G. Holzman, "The model checker Spin", IEEE Transactions on Software Engineering, May 1997.

K. Bang et. al., "Comments on "The model checker Spin"", IEEE Transactions on Software Engineering, June 2001.

D. Latella et. al., "Automatic verification of a behavioural subset of UML statechart diagrams using the SPIN model-checker", Formal Aspects of Computing, 1999.

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Tu 1/22 J. Guo SpecC presentations:

J. Zhu et. al., "Compiling SpecC for simulation", ASPDAC01

L. Cai et. al., "Introduction of system level architecture exploration using the SpecC methodology", ISCAS01

 

www.specc.gr.jp/eng/index.htm

www.ics.uci.edu/~specc

D. Jansen, "SpecC for Beginners: The example of a sounding Dice", UCI Technical Report ICS-TR-00-14

D. Gajski et. al., "The SpecC Methodology", UCI Technical Report ICS-TR-99-56

R. Domer et. al., "Reuse and protection of intellectual property in the SpecC system", ASPDAC00

 

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Th 1/24 A. Buyukkurt

System C presentations:

G. Arnout, "SystemC standard", ASPDAC00

S. Swan, "An Introduction to System-Level Modeling in SystemC 2.0" (OSCI internal documentation)

 

systemc.org

W. Mueller et. al., " The simulation semantics of SystemC", DATE01

G. Economakos et. al., "Behavioral synthesis with SystemC" DATE01

S. Liao et. al., "An Efficient Implementation of Reactivity for Modeling Hardware",  DAC97

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H. Hsieh Programming in Metropolis HTML

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Tu 1/29 Students Project Progress Presentation. 10 minutes each person-project.  Presentation should include background, plan of attack, expected result, and progress so far.
Th 1/31 L. Jin Superlog presentations:

P. Flake et. al., "Superlog, a unified design language for system-on-a-chip", ASPDAC00

S. Boyd, "Ethernet over SONET (EoS) device verification - leveraging SUPERLOG", Electronic Engineering, May 2001.

superlog.org

"Superlog Tutorial" (presentation)

 

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H. Hsieh Sample paper in LaTeX Gzipped

Tu 2/5 S. Dhirakaosal Xtensa presentations:

R. Gonzalez et. al., "Xtensa: A Configurable and Extensible Processor", IEEE Micro00

A. Wang et. al., "Hardware Instruction set Configurability for System-on-Chip Processors", DAC01

tensilica.com

J. Sanghavi et. al., "Estimation of speed, area, and power of parameterizable, soft IP", DAC01

G. Ezer, "Xtensa with user defined DSP coprocessor microarchitectures", ICCD00

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Th 2/7 A. McDaniel System level power reduction presentations:

V. Tiwari et. al., "Power Analysis of Embedded Software: A First Step Towards Software Power Minimization", IEEE Transactions on VLSI systems December 1994.

L. Nachtergaele et. al., "System and architecture-level power reduction of microprocessor-based communication and multi-media application", ICCAD00

M. Macci et. al. "High-Level Power Modeling, Estimation and Optimization", DAC97

D. Brooks et. al., Wattch: A Framework for Architectural-Level Power ANalysis and OPtimizations, ISCAS00

T. Mudge, "Power: A First Class Architectural Design Constraint", IEEE Computer, 2001

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Tu 2/12 Open-Book Quiz, cover everything above in this column
Th 2/14  X. Chen Formal Verification Algorithms:

G. Holzman, "The model checker Spin", IEEE Transactions on Software Engineering, May 1997.

E. Clarke, et. al. "Automatic verification of finite-state concurrent systems using temporal logic specifications". ACM Transactions on Programming Languages and Systems, 8(2):244--263, 1986.

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Tu 2/19 A. Buyukkurt Embedded Software for control:

Y. Li et. al. "Performance analysis of embedded software using implicit path enumeration",  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Dec. 1997, vol. 16, (no.12):1477-87

Balarin et. al. "Synthesis of software programs for embedded control applications", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.18, (no.6), IEEE, June 1999. p.834-49

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Th 2/21 S. Dhirakaosal Embedded Software for data processing:

P. Paulin et. al.,  "Embedded software in real-time signal processing systems: application and architecture trends", Proceedings of the IEEE, vol. 85, (no.3), IEEE, March 1997, p. 419-35

G. Goossens et. al., "Embedded software in real-time signal processing systems: design technologies",  Proceedings of the IEEE, vol. 85, (no.3), IEEE, March 1997, p. 436-54

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Tu 2/26 J. Guo Scheduling:

C. Liu et. al. "Scheduling Algorithm for Multiprogramming in a Hard-Real-Time Environment". Journal of the ACM, Jan 1973.

Balarin, et. al.,  "Scheduling for Embedded Real-Time Systems"
IEEE Design and Test of Computers 1998.  

Th 2/28 L. Jin More Power Consideration:

E. Macii et. al., "High-Level Power Modeling, Estimation and Optimization",  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.17, (no.11), IEEE, Nov. 1998. p.1061-79.

D. Brooks et. al., "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations", Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201), (Proceedings of 27th International Symposium on Computer Architecture 


Tu 3/5 F. Chen Parameterized architecture and dataflow synthesis:

T. Givargis et. al., "Evaluating power consumption of parameterized cache and bus architectures in system-on-a-chip designs". IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.9, (no.4), IEEE, Aug. 2001. p.500-8

R. Rinker et.al., "An automated process for compiling dataflow graphs into reconfigurable hardware". IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.9, (no.1), IEEE, Feb. 2001. p.130-9.

Th 3/7 Class Cancelled.  Work on your project!!!

Tu 3/12 A. McDaniel

Architecture issues:

D. Burger et. al., "The SimpleScalar tool set, version 2.0", University of Wisconsin-Madison Computer Sciences Department Technical Report #1342, June, 1997.

M. Hall et. al, "Maximizing multiprocessor performance with the SUIF compiler". IEEE Computer, vol.29, (no.12), Dec. 1996. p.84-9.

 
Th 3/14 Students Final Project Presentations:  20 minutes each person-project

 

Individual Projects

Project may be done in a team of 1 or 2.  A list of proposed projects follows.  You may also propose your own project, as long as the topic falls within the confine of the course and it has comparable depth as the other projects.  Project request is on a first-come-first-serve basis.  You are encouraged to send me e-mail frequently about your progress or any question you may have throughout the quarter.  The idea is that the result of the project, possibly with one more quarter of independent study by one student, will have enough technical content for a conference or workshop presentation.

Project Deadlines are: 

1/17 Thursday noon Deadline for project request.  Finalized project assignment.
1/29 Tuesday (in class) Project Progress Presentation 10 minutes each person-project
2/7 Thursday (in class) 1st draft of project report (~2 pages), background, expected result, plan, progress
2/12-2/14 to be scheduled Project Progress Demonstration I, 1 hour each project
2/26 Tuesday (in class) 2nd draft of project report (~4 pages), background, expected result, plan, progress
2/26-3/1 to be scheduled Project Progress Demonstration II, 1 hour each project
3/14 Thursday (in class) Final Project Presentation, 20 minutes each person-project
3/19 Wednesday  (midnight) Final Report Preview (please send me what you have at that point)
3/22 Friday (midnight, penalty for late report) Final Project Report (~8 pages "conference format": 2 column, 11pt, single space)

1) Modeling heterogeneous semantics in Metropolis

2) Simulation and Formal Verification of Metropolis designs using SPIN

3) Simulation and Formal Verification of Metropolis action automata using SPIN

4) Generating Simulation monitor for LOC using SPIN

5) Simulation of Metropolis design using SpecC design environment

6) Simulation and Formal Verification of Metropolis action automata using SMV

 

Project Descriptions

1) Modeling heterogeneous semantics in Metropolis:

Students: S. Dhirakaosal and A. Buyukkurt

Goal:
-----
Metropolis heterogeneous system design framework has within it a metamodel language which can be used to unambiguously model other models of computation.  This project studies variety of semantics of computation and communication often used in applications of embedded systems, and identifies how they can be modeled with the Metropolis meta-model. Metamodel allows one to model
different semantics uniformly using a common set of building blocks. This capability is essential in synthesis and verification, where heterogeneous components must be compared and their interaction needs to be analyzed. The project considers the Finite State Machine, Synchronous Data Flow,  Discrete Event, and Process Network models of computations.  The project is to construct a "library" for each MOC so design within a model of computation can be represented clearly using the elements of the library.  Since these semantics are also supported in Ptolemy II, a translator should then be built to convert designs in Ptolemy II (there are many) into Metropolis Metamodel (MMM) using appropriate library.

Procedure:
----------
1) Study and understand MMM.
2) Study and understand FSM, SDF, DE, and PN and understand how they are implemented in Ptolemy II
3) Document carefully how each MOC can be modeled by defining a library of constructs and functions for each MOC
4) Write a "possibly JAVA" program to interface with Ptolemy II so designs written in those two domains can be translated into MMM. There are numerous demo design already exists that can be used to test your translator.
5) Test out the translator by simulating within Ptolemy II and by manually
trace the generated MMM files (if they are ready, you may also simulate with JAVA, SystemC, SpecC, or Spin simulator)
(extra) Do the above for other domains chosen from the following: CSP, DDE, DT, or Giotto.

Expected product:
-----------------
Careful documentation of the metropolis libraries for the domains, plus a fully functional translator for the examples within Ptolemy II.

Reference:
----------
* Ptolemy website: ptolemy.eecs.berkeley.edu
* "Metropolis: Design Environment for Heterogeneous Systems", Metropolis Project Team, Cadence Technical Conference 2001.
* "Modeling and Designing Heterogeneous Systems", F. Balarin, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi, and Y. Watanabe.
* "The Metropolis Meta-Model, version 0.2.7" The Metropolis Project Team

 

2) Simulation and Formal Verification of Metropolis designs using SPIN

Students: J. Guo and L. Jin

Goal:
-----

SPIN is a widely distributed tool for software verification developed at Bell Labs. This project will make it possible to verify designs captured in Metropolis using SPIN. Both Metropolis and SPIN use linear temporal logic to write properties to be verified. They both use single specification languages, but with different concerns. The challenge is to represent designs captured in Metropolis using SPIN's specification language, PROMELA. In this project, the semantics of the two languages will be carefully analyzed, and a
Metropolis backend tool will be written in order to generate PROMELA from Metropolis.

Procedure:
----------
1) Study and understand MMM.
2) Study and understand Promela and SPIN.
3) Document carefully and unambiguously how each Metropolis metamodel constructs can be modeled by Promela. If there are constructs that can not be translated, explain precisely why. You will need to explain especially what you do with the non-determinism in MMM, as well as the scheduling that may not be supported directly by SPIN.
5) Write a (probably JAVA) program to interface Metropolis AST, so designs written in MMM can be translate into Promela. Spin already accept LTL as properties. You may ignore LOC and ELOC constraints for now.
6) Test out the translator and show through examples that the translation is correct. Simulate the example in SPIN, and perform a simple verification case study.
(extra) Translate LOC and ELOC into monitors for simulation within SPIN, and if you can, translate LOC and ELOC into properties to be checked within SPIN.  For the properties that you cannot, explain why.

Expected product:
-----------------
Careful documentation of the translation from MMM to Promela, plus a fully functional translator. You will also need to document a careful case study of simulation and formal verification.

Reference:
----------
* SPIN website: http://netlib.bell-labs.com/netlib/spin/whatispin.html
* "Metropolis: Design Environment for Heterogeneous Systems", MetropolisProject Team, Cadence Technical Conference 2001.
* "Modeling and Designing Heterogeneous Systems", F. Balarin, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi, and Y. Watanabe.
* "The Metropolis Meta-Model, version 0.2.6" The Metropolis Project Team.


3) Simulation and Formal Verification of Metropolis action automata using SPIN

Students: F. Chen and X. Chen

Goal:
-----
The semantics of Metropolis metamodel is defined by a set of "action automata" and associated datapath. For each syntactic construct in the meta-model, an automaton specifying its control semantic is defined. The goal of this project is to automatically generate these automata and the associated datapath for a given meta-model netlist. The automata and the datapath would be represented in Promela, the entry language for SPIN.  SPIN is a widely distributed tool for software verification developed at Bell Labs. In this project, the semantics of the two languages will be carefully analyzed, and a Metropolis backend tool will be written in order to generate PROMELA for Metropolis action automata.


Procedure:
----------
1) Study and understand MMM, especially how action automata are generated from MMM
2) Study and understand Promela and SPIN.
3) Document carefully and unambiguously how each Metropolis action automata constructs can be modeled by Promela. If there are constructs that can not be translated, explain precisely why. You will need to explain especially what you do with the non-determinism in metropolis action automata.
5) Write a (probably JAVA) program to interface Metropolis AST, so designs written in MMM can be translate into Promela.
6) Test out the translator and show through examples that the translation is correct. Simulate the example in SPIN (what about non-determinism?), and perform a simple verification case study.
(extra) Build a semantic checker on top of your tool.  Given a Metropolis simulation trace, can you verify the trace is semantically correct according to the action automata?  (extra extra) what is the minimum elements required to be in the simulation trace for you to make that determination?  Clearly you need more than just primary I/O.  You will probably need to think about observability/controllability

Expected product:
-----------------
Careful documentation of the translation from Metropolis action automata to Promela, plus a fully functional translator. You will also need to document a careful case study of simulation and formal verification.

Reference:
----------
* SPIN website: http://netlib.bell-labs.com/netlib/spin/whatispin.html
* "Metropolis: Design Environment for Heterogeneous Systems", MetropolisProject Team, Cadence Technical Conference 2001.
* "Modeling and Designing Heterogeneous Systems", F. Balarin, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi, and Y. Watanabe.
* "The Metropolis Meta-Model, version 0.2.6" The Metropolis Project Team.

4) Generating Simulation monitor for LOC using SPIN

Students: TBA

Goal:
-----
LOC (Logic Of Constraints) is used to specified a set of constraints particularly useful in embedded system design. It is strictly more powerful than prepositional logics, (or Linear Temporal Logics, for that matter), so it is not possible to represent constraints in LOC with Finite State Automata.  However, it is possible to generate a monitor to test whether or not a particular constraint is satisfied during simulation. This project is to define a translation from constraints in LOC to simulation monitor in Promela.  It is mean to work for any Promela simulation whether they are for embedded system or general software/protocol design.

Procedure:
----------
1) Study and understand LOC
2) Study and understand Promela and SPIN.
3) Document carefully and unambiguously how each LOC constraint can be translated into a simulation monitor written in Promela, and how this simulation monitor can be used during simulation of Promela codes.  . If there are constraints that can not be translated, explain precisely why..
5) Write a program (including a parser) that will take any constraints in LOC and output a correct Promela simulation monitor. 
6) Test out the translator and show through examples that the translation is correct. Simulate an example in SPIN, and show how the simulation monitor works.
(extra) Identify subset of LOC that is amendable to formal verification within SPIN.  Augment your translator to translate those constraints into LTL or FSM monitor so they can be formally verified.

Expected product:
-----------------
Careful documentation of the translation from LOC contraints to Promela simulation monitor, plus a fully functional translator. You will also need to document a careful case study of simulation with with these monitors.

Reference:
----------
* SPIN website: http://netlib.bell-labs.com/netlib/spin/whatispin.html
* "Metropolis: Design Environment for Heterogeneous Systems", MetropolisProject Team, Cadence Technical Conference 2001.
* "Modeling and Designing Heterogeneous Systems", F. Balarin, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi, and Y. Watanabe.
* F. Balarin et. al., "Constraints Specification at Higher Levels of Abstraction", International High-Level Design Validation and Test Workshop, Nov 2001.

 

5) Simulation of Metropolis design using SpecC design environment

Student: A. McDaniel

Goal:
-----

SpecC is developed initially by Prof. Gajski of UC-Irvine and is poised to be one of the major competitor to SystemC as a system level design language for embedded systems.  Like SystemC, it is based on C/C++ constructs and capable to model any specification for embedded application.  A simulator and a reference compiler is freely available for SpecC, so this project will attempt to simulate Metropolis constructs and Metropolis designs using SpecC.  In this project, the semantics of the two languages will be carefully analyzed, and a Metropolis backend tool will be written in order to generate SpecC from Metropolis.

Procedure:
----------
1) Study and understand MMM.
2) Study and understand SpecC, SpecC Simulator, and SpecC reference compiler
3) Document carefully and unambiguously how each Metropolis metamodel constructs can be modeled by SpecC. If there are constructs that can not be translated, explain precisely why. You will need to explain especially what you do with the non-determinism in MMM, as well as the scheduling that may not be supported directly by SpecC.
5) Write a (probably JAVA) program to interface Metropolis AST, so designs written in MMM can be translate into SpecC.  You may ignore LTL, LOC and ELOC constraints for now.
6) Test out the translator and show through examples that the translation is correct. Simulate some test examples in SpecC.
(extra) What can you do with LTL, LOC and ELOC for SpecC?  How about simulation monitors?  Write a translator to translate LTL, LOC, and probably some ELOC (how do you do "there exists"?) into SpecC simulation monitor that if a violation of the constraints occurred during simulation, a flag will be raised.

Expected product:
-----------------
Careful documentation of the translation from MMM to SpecC, plus a fully functional translator. You will also need to document a careful case study of simulation.

Reference:
----------
* "Metropolis: Design Environment for Heterogeneous Systems", MetropolisProject Team, Cadence Technical Conference 2001.
* "Modeling and Designing Heterogeneous Systems", F. Balarin, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi, and Y. Watanabe.
* "The Metropolis Meta-Model, version 0.2.6" The Metropolis Project Team.
* A. Gerstlauer et. al., "System Design: A practical guide with SpecC", Kluwer Academic Publishers
* "SpecC language reference manual v1.0"
* www.ics.uci.edu/~specc

 

6) Simulation and Formal Verification of Metropolis action automata using SMV

Goal:
-----
The semantics of Metropolis metamodel is defined by a set of "action automata" and associated datapath. For each syntactic construct in the meta-model, an automaton specifying its control semantic is defined. The goal of this project is to automatically generate these automata and the associated datapath for a given meta-model netlist. The automata and some aspect of the datapath would be represented in SMV, the entry language for Symbolic Model Verifier and intermediate format for Formal Check from Cadence Design systems.  In this project, the semantics of the two languages will be carefully analyzed, and a Metropolis backend tool will be written in order to generate SMV for Metropolis action automata.


Procedure:
----------
1) Study and understand MMM, especially how action automata are generated from MMM
2) Study and understand SMV.
3) Document carefully and unambiguously how each Metropolis action automata constructs can be modeled by SMV. If there are constructs that can not be translated, explain precisely why. You will need to explain especially what you do with the datapath portion of the design.  Some abstract will probably be needed, write down your abstraction.
5) Write a (probably JAVA) program to interface Metropolis AST, so designs written in MMM can be translate into SMV.
6) Test out the translator and show through examples that the translation is correct.  Perform a simple verification case study.
(extra) Build a semantic checker on top of your tool.  Given a Metropolis simulation trace, can you verify the trace is semantically correct according to the action automata?  Be careful that you handle your datapath abstraction conservatively  (extra extra) what is the minimum elements required to be in the simulation trace for you to make that determination?  Clearly you need more than just primary I/O.  You will probably need to think about observability/controllability

Expected product:
-----------------
Careful documentation of the translation from Metropolis action automata to SMV, plus a fully functional translator. You will also need to document a careful case study of  formal verification.

Reference:
----------
* "Symbolic Model Verifier", Ken McMillen.(www-cad.eecs.berkeley.edu/~kenmcmil/smv)
* "Metropolis: Design Environment for Heterogeneous Systems", MetropolisProject Team, Cadence Technical Conference 2001.
* "Modeling and Designing Heterogeneous Systems", F. Balarin, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi, and Y. Watanabe.
* "The Metropolis Meta-Model, version 0.2.7" The Metropolis Project Team.