UCR CS220: Synthesis of Digital Systems

CS220 covers the synthesis and simulation of digital systems. Topics include synthesis at the system, behavioral, register-transfer, and logic levels; application-specific processors; simulation; and emerging system-on-a-chip design methodologies.

Course information

Lecture Topics

Homeworks

• Homework 1
• Homework 2
• Homework 3
• Homework 4
• Homework 5

Individual Projects

Project may be done in a team of 1 or 2.  A list of proposed projects follows.  You may also propose your own project, as long as the topic falls within the confine of the course and it has comparable depth as the other projects.  Project request is on a first-come-first-serve basis, though some of the projects may be pre-assigned due to the previous expertise.  You are encouraged to send me e-mail frequently about your progress or any question you may have throughout the quarter.  There are also four scheduled project group meeting in my office throughout the quarter, as well as a project progress report for checking on your progress.  The idea is that the result of the project, possibly with one more quarter of independent study by one student, will have enough technical content for a conference or workshop presentation.

Project deadlines are: 

1. Modeling Heterogeneous Semantics in Metropolis 
2. Simulation and Formal Verification of Metropolis Designs Using SPIN
3. Generating Simulation Monitor from LOC into Promela
4. Generating Metropolis Process from Dataflow Language CAL
5. On-line Containment Checking for Abstract Behaviors
6. Minimization of Ternary Matching Tables
7. Architectural Level Functional Equivalence of Implementations Based on YAPI Specifications
8. Run Time Re-synthesis for Embedded FPGA designs

Project Descriptions

1) Modeling Heterogeneous Semantics in Metropolis

Students: Betul Buyukkurt and Lingling Jin

Goal:
-----
Metropolis heterogeneous system design framework has within it a metamodel language which can be used to unambiguously model other models of computation.  This project studies a variety of semantics of computation and communication often used in applications of embedded systems, and identifies how they can be modeled with the Metropolis meta-model (MMM). Metamodel allows one to model different semantics uniformly using a common set of building blocks. This capability is essential in synthesis and verification, where heterogeneous components must be compared and their interaction needs to be analyzed. The project considers the Synchronous Data Flow, Process Network, Finite State Machine, Petri-net, YAPI, and Verilog/VHDL (Discrete Event) models of computations.  The project is to device a methodology/ medium library for each MOC so design within a model of computation can be represented clearly using the methodology and the elements of the library.  It is preferred to have the designs represented in MMM with MOC independent processes and different medium and constraints for different MOCs. The difference in medium and constraints used should reflect the similarity and difference between the MOCs.

Procedure:
----------

1. Study and understand MMM.
2. Study and understand SDF, Process Network, FSM, Petri-net, YAPI, and Verilog/VHDL, and document carefully how each MOC can be modeled by defining a library of medium and constraints and a methodology for each MOC.
3. Show how designs for each MOC from the literatures can be reimplemented in Metropolis using your library and methodology. The resulting MMM implementation should be parsed by Metropolis parser.
4. (A+) Program a sufficient MOC finder that will parse through the abstract syntax tree (AST) and identify which MOC the design conforms to.

Expected product:
-----------------
Careful documentation of the metropolis media and constraints libraries and methodologies for the MOCs, plus reimplementation of many examples from the literatures.  There should also be a preliminary study of a MOC finder and programming for identifying designs conforming to a particular MOCs.

Reference:
----------

• "Modeling and Designing Heterogeneous Systems", F. Balarin, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi, and Y. Watanabe. 
• "Modeling Heterogeneous Semantics in Metropolis", Buyukkurt and Dhirakaosal, CS269 project report.
• "The Metropolis Meta-Model, version 0.2.7" The Metropolis Project Team.
• Ptolemy website: ptolemy.eecs.berkeley.edu
• Dwivedi, B.K.; Hoogerbrugge, J.; Stravers, P.; Balakrishnan, M. "Exploring design space of parallel realizations: MPEG-2 decoder case study". Ninth International Symposium on Hardware/Software Codesign. CODES 2001 
• De Kock, E.A.; Essink, G.; Smits, W.J.M.; Van Der Wolf, P.; Brunel, J.-Y.; Kruijtzer, W.M.; Lieverse, P.; Vissers, K.A. "YAPI: application modeling for signal processing systems". Proceedings 2000. Design Automation Conference. 
• http://www.daimi.au.dk/PetriNets/introductions/

2) Simulation and Formal Verification of Metropolis Designs Using SPIN

Students: Xi Chen and Fang Chen

Goal:
-----

SPIN is a widely distributed tool for software verification developed at Bell Labs. This project will make it possible to verify designs captured in Metropolis using SPIN. The challenge is to represent designs captured in Metropolis using SPIN's specification language, PROMELA. In this project, the semantics of the two languages will be carefully analyzed, and a Metropolis backend tool will be written in order to generate PROMELA from Metropolis.

Procedure:
----------

1. Study and understand MMM.
2. Study and understand Promela and SPIN.
3. Document carefully and unambiguously how each Metropolis metamodel constructs can be modeled by Promela. If there are constructs that can not be translated, explain precisely why. You will need to explain especially what you do with the non-determinism in MMM, as well as the scheduling that may not be supported directly by SPIN.
4. Write a (probably JAVA) program to interface Metropolis AST, so designs written in MMM can be translate into Promela. Spin already accept LTL as properties. You may ignore LOC and ELOC constraints for now.
5. Test out the translator and show through examples that the translation is correct. Simulate the example in SPIN, and perform a simple verification case study.
6. Translate LTL from MMM to be read in by SPIN.  Keep in mind that LTL in MMM is used as a "behavior limiter" while in SPIN, LTL is used to represent "constraints to be satisfied".
7. (A+) Translate LOC and ELOC into monitors for simulation within SPIN, and if you can, translate LOC and ELOC into properties to be checked within SPIN.  For the properties that you cannot, explain why, or
8. (A+) Run FV tool in Spin to check for containment relationship between a more refined specification against its abstraction.

Expected product:
-----------------
Careful documentation of the translation from MMM to Promela, plus a fully functional translator. You will also need to document a careful case study of simulation and formal verification.  Some preliminary study on how to deal with LOC and ELOC should also be attempted, or a case study of abstraction relation verification.

Reference:
----------

• "Modeling and Designing Heterogeneous Systems", F. Balarin, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi, and Y. Watanabe.
• "Simulation and Formal Verification of Metropolis designs using SPIN", Guo and Jin, CS269 project report.
• "Simulation and Formal Verification of Metropolis Action Automata using SPIN", Chen and Chen, CS269 project report.
• "The Metropolis Meta-Model, version 0.2.7" The Metropolis Project Team.
• SPIN website: http://netlib.bell-labs.com/netlib/spin/whatispin.html.
• The metroplis metamodel compiler (tared and gzipped)

3) Generating Simulation Monitor from LOC into Promela

Students: Artur Kedzierski

Goal:
-----
LOC (Logic Of Constraints) is used to specified a set of constraints particularly useful in embedded system design. It is strictly more powerful than prepositional logics, (or Linear Temporal Logics, for that matter), so it is not possible to represent constraints in LOC with Finite State Automata.  However, it is possible to generate a monitor to test whether or not a particular constraint is satisfied during simulation. This project is to define a translation from constraints in LOC to simulation monitor in Promela.  It is mean to work for any Promela simulation whether they are for embedded system or general software/protocol design.

Procedure:
----------
1) Study and understand LOC.
2) Study and understand Promela and SPIN.
3) Document carefully and unambiguously how each LOC constraint can be translated into a simulation monitor written in Promela, and how this simulation monitor can be used during simulation of Promela codes.  If there are constraints that can not be translated, explain precisely why..
5) Write a program (including a parser) that will take any constraints in LOC and output a correct Promela simulation monitor. 
6) Test out the translator and show through examples that the translation is correct. Simulate an example in SPIN, and show how the simulation monitor works.
(A+) Identify subset of LOC that is amendable to formal verification within SPIN.  Augment your translator to translate those constraints into LTL or FSM monitor so they can be formally verified.

Expected product:
-----------------
Careful documentation of the translation from LOC constraints to Promela simulation monitor, plus a fully functional translator. You will also need to document a careful case study of simulation with with these monitors.

Reference:
----------
* SPIN website: http://netlib.bell-labs.com/netlib/spin/whatispin.html
* "Metropolis: Design Environment for Heterogeneous Systems", MetropolisProject Team, Cadence Technical Conference 2001.
* "Modeling and Designing Heterogeneous Systems", F. Balarin, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi, and Y. Watanabe.
* F. Balarin et. al., "Constraints Specification at Higher Levels of Abstraction", International High-Level Design Validation and Test Workshop, Nov 2001.

4) Generating Metropolis Process from Dataflow Actor Language CAL

Students:  Dinesh Suresh and Yun Zheng

Goal:
-----
Metropolis heterogeneous system design framework has within it a metamodel language which can be used to unambiguously model other models of computation.  CAL is a language devised by the Ptolemy group to represent actors, which may correspond roughly to processes in Metropolis. This project studies the ways CAL actors can be translated into Metropolis processes.  A functioning translator is the goal of this project, since a "semi-functional" translator already exists from CAL to JAVA and C so that a  translator to Metropolis processes may be achieved by suitable modification of the existing translators.

Procedure:
----------

1. Study and understand MMM.
2. Study and understand CAL.
3. Document carefully how each CAL construct can be modeled as MMM process.
4. Show how demo CAL actors (there are many) may be reimplemented as MMM process.  The resulting MMM implementation should be parsed by Metropolis parser.
5. Program a translator from CAL actors to MMM processes
6. Utilize CAL translated processes in Metropolis in writing a complete design.
7. (A+) Expand the translator to translate also the netlist so that the complete design in Ptolemy can be translated int MMM.

Expected product:
-----------------
Careful documentation of CAL2MMM translator, as well as a functioning translator, plus some case study using the translator.

Reference:
----------

• "Modeling and Designing Heterogeneous Systems", F. Balarin, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi, and Y. Watanabe.
• "Modeling Heterogeneous Semantics in Metropolis", Buyukkurt and Dhirakaosal, CS269 project report.
• "The Metropolis Meta-Model, version 0.2.7" The Metropolis Project Team.
• CAL reference manual at: http://www.gigascale.org/caltrop/
• Ptolemy website: ptolemy.eecs.berkeley.edu

5) On-line Containment Checking for Abstract Behaviors

Students: 

Goal:
-----
Metropolis heterogeneous system design framework has within it a metamodel language which can be used to unambiguously model other models of computation.  Naturally, different MOCs (and sometime the same MOC) may be used to represent different levels of design abstraction.  This project deals with verification of the trace containment of one level (refined) of abstraction against another level (abstracted) level of abstraction.  Clearly, a theoretical backing exists for this problem and formal verification tools may be used to prove the trace containment.  However, automatic formal verification tools suffers greatly from complexity problem.  This project focus on simulation methods to demonstrate that the lower level is indeed a refinement of the upper level, with respect to the single simulation trace.  The approach to this project is to use SPIN, or any other framework with both simulation and formal verification capability, to demonstrate such a single trace containment paradigm is feasible and meaningful.

Procedure:
----------

1. Study and understand MMM.
2. Study and understand SPIN.
3. Demonstrate through a simple example that a lower level simulation can be a refinement with respect to a single simulation trace.  You need to first write both example in MMM, then code up equivalents in Promela to be read into SPIN.  A  possible example will be a finite length FIFO queue with two input.  The abstract representation will non-deterministically choose between the input while the refined representation will also choose the higher priority one.  In fact, the "double stream" example will be a good starting point.
4. Demonstrate with a realistic design.  (possibly mpeg decoder)
5. Perform optimization on the decision procedure, possibly with backward traversal, i.e. the desired output is known from the trace of the refined representation, so start with that output and trace backward to figure out the non-determinism resolution for the abstracted representation.
6. (A+) code up the decision procedure.

Expected product:
-----------------
Careful documentation of a case study of the realistic design, plus simple methodology and programs that perform this containment check.  In addition, an optimization algorithm to make the decision procedure heuristically more efficient.

Reference:
----------

• "Modeling and Designing Heterogeneous Systems", F. Balarin, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi, and Y. Watanabe.
• "The Metropolis Meta-Model, version 0.2.7" The Metropolis Project Team.
• SPIN website: http://netlib.bell-labs.com/netlib/spin/whatispin.html

6) Minimization for Ternary Matching Tables

Students: Phillip Hoang and Suvidhean Dhirakaosal

Goal:
-----

Routing lookup function is essential in network processing application and will increasingly become a bottleneck as number of Internet Protocol addresses continue to increase.  Ternary Content Addressable Memory has been utilized as a mean for fast IP address forwarding lookup by dedicated hardware.  In fact, a single cycle lookup at around 100 Million lookup per second as achieved by commercial TCAM today.  The drawback of TCAM is that  its cost and power usage is directly related to the table size, and a raw table today range in size between 32K and 64K, and can easily make it beyond 128K in the near future.  A simple approach of table compaction using 2-level logic synthesis technique can compact the table in half.  This project seeks to reduce the size of the table further by using more aggressive logic synthesis technique, while keeping update to the table in a timely manner feasible.  This will most likely involve a new reconfigurable architecture tailored specific to this problem.

Procedure:
----------

1. Understand the IP routing problem, and how 2-level logic minimization can be used to compact the table.
2. Extend the approach with output encoding, conduct experiments to validate the approach, including algorithm on updating the table.
3. Extend the approach with prefix-expansion and output encoding,  conduct experiments.
4. Extend the approach with also input encoding and phase assignment, conduct experiments.
5. Extend the approach to utilize multiple-level logic synthesis, explore using hierarchical TCAM or general FPGA for IP routing.
6. (A+) extend the approach to general CAM problem with large database lookup.

Expected product:
-----------------

Codes and script for utilizing espresso and sis to compact the table, as well as coded algorithm for updates.

Reference:
----------

• http:\\www.idt.com
• http:\\www.sibercore.com
• Huan Liu "Routing table compaction in ternary CAM". IEEE Micro, vol.22, (no.1), IEEE, Jan.-Feb. 2002
• Srinivasan, V.; Varghese, G. "Fast address lookups using controlled prefix expansion". ACM Transactions on Computer Systems, vol.17, (no.1), ACM, Feb. 1999
• Ruiz-Sanchez, M.A.; Biersack, E.W.; Dabbous, W. Survey and taxonomy of IP address lookup algorithms. IEEE Network, vol.15, (no.2), IEEE, March-April 2001

7) Architectural Level Functional Equivalence of Implementations Based on YAPI Specification

Students: Nikhil Aggarwal

Goal:
-----

As complexity of digital design grows, it is becoming more and more attractive to be able to work from a very high level of abstraction.  Fundamental mode assumption has made it possible to design hardware circuits from VHDL or Verilog, so that the functional equivalence of the circuits generated from the same high level specification is well defined and relatively easy to verify.  The same assumption does not exist (or rather, has not been proposed) for system level design.  The functional analysis at the architectural level is therefore often ad hoc, or at best, design dependent.  For designs based on Codesign Finite State Machine network, Synchronous Equivalence and system level Synchronous Assumption has been proposed as the equivalence notion and necessary assumption.  The assumption make it possible to analyze the equivalence efficiently at the system level, without resorting to general formal verification algorithm.  This project looks to established similar notion for designs based on YAPI, a design representation that is a slight extension to Kahn's process network.

Procedure:
-----------

1. Understand YAPI and design example in YAPI.
2. Understand Synchronous Equivalence, CFSM, and abstract communication analysis.
3. Define assumption and architectural equivalence notion for implementations of YAPI specification.  Devise efficient analysis method (may be non-exact but should at least be conservative).
4. Demonstrate with real-life YAPI examples
5. Program a tool to automatically analyze YAPI implementations and return an answer as to whether or not they are functionally equivalent
6. (A+) Extend the idea to even more general MOC such as SystemC or any other "system level" design language.

Expected product:
------------------

Careful definition of assumption and equivalence and efficient analysis method which may be non-exact but must be conservative.  Careful case study with a real-life YAPI design (possibly MPEG decoder), and a tool which perform such analysis for YAPI implementations


Reference:
----------

• De Kock, E.A.; Essink, G.; Smits, W.J.M.; Van Der Wolf, P.; Brunel, J.-Y.; Kruijtzer, W.M.; Lieverse, P.; Vissers, K.A. YAPI: application modeling for signal processing systems. Proceedings 2000. Design Automation Conference. 
• Dwivedi, B.K.; Hoogerbrugge, J.; Stravers, P.; Balakrishnan, M. "Exploring design space of parallel realizations: MPEG-2 decoder case study". Ninth International Symposium on Hardware/Software Codesign. CODES 2001

• Hsieh, H.; Balarin, F.; Lavagno, L.; Sangiovanni-Vincentelli, A. Synchronous approach to the functional equivalence of embedded system implementations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.20, (no.8), IEEE, Aug. 2001

8) Run-Time Re-synthesis for Embedded FPGA Designs

Students: 

Goal:
-----

The idea of dynamic translated execution has intrigued researchers since the early 90's.  HP Dynamo is one such project that allows the OS to dynamically optimize the software base on run time information.  Earlier this year, Xilinx delivered their Virtex II Pro chip which, in addition to flexible reconfiguration, has embedded up to for PowerPCs for computation that is not well suited for FPGA implementation.  This project seeks to understand the possibility of Dynamo style reconfiguration for FPGA fabrics, where the ultimate goal is to have of of PowerPC chip profile the run time information and based on that information, re-synthesize and reconfiguration Virtex for higher performance and lower power usage.

Procedure:
-----------

1. Understand Dynamo.
2. Understand Virtex.
3. Propose a methodology to apply dynamic reconfiguration to Virtex.
4. Perform a case study on real-life example through simulation.
5. (A+) Demonstrate through actually running Virtex II Pro and show how your methodology improve performance and power usage.

Expected product:
------------------

Case study of dynamic reconfiguration on Virtex.

Reference:
----------

• http://www.hpl.hp.com/cambridge/projects/Dynamo/
• http://www.xilinx.com
• "Reconfigurable Computing: a Survey of Systems and Software" K. Compton and S. Hauck. to appear in ACM Computing Surveys, 2002.

9) Simulation and Formal Verification of Metropolis Action Automata Using SMV

Goal:
-----
The semantics of Metropolis metamodel is defined by a set of "action automata" and associated datapath. For each syntactic construct in the meta-model, an automaton specifying its control semantic is defined. The goal of this project is to automatically generate these automata and the associated datapath for a given meta-model netlist. The automata and some aspect of the datapath would be represented in SMV, the entry language for Symbolic Model Verifier and intermediate format for Formal Check from Cadence Design systems.  In this project, the semantics of the two languages will be carefully analyzed, and a Metropolis backend tool will be written in order to generate SMV for Metropolis action automata.

Procedure:
----------
1) Study and understand MMM, especially how action automata are generated from MMM
2) Study and understand SMV.
3) Document carefully and unambiguously how each Metropolis action automata constructs can be modeled by SMV. If there are constructs that can not be translated, explain precisely why. You will need to explain especially what you do with the datapath portion of the design.  Some abstract will probably be needed, write down your abstraction.
5) Write a (probably JAVA) program to interface Metropolis AST, so designs written in MMM can be translate into SMV.
6) Test out the translator and show through examples that the translation is correct.  Perform a simple verification case study.
(A+) Build a semantic checker on top of your tool.  Given a Metropolis simulation trace, can you verify the trace is semantically correct according to the action automata?  Be careful that you handle your datapath abstraction conservatively  (extra extra) what is the minimum elements required to be in the simulation trace for you to make that determination?  Clearly you need more than just primary I/O.  You will probably need to think about observability/controllability

Expected product:
-----------------
Careful documentation of the translation from Metropolis action automata to SMV, plus a fully functional translator. You will also need to document a careful case study of  formal verification.

Reference:
----------
* "Symbolic Model Verifier", Ken McMillen.(www-cad.eecs.berkeley.edu/~kenmcmil/smv)
* "Metropolis: Design Environment for Heterogeneous Systems", MetropolisProject Team, Cadence Technical Conference 2001.
* "Modeling and Designing Heterogeneous Systems", F. Balarin, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi, and Y. Watanabe.
* "The Metropolis Meta-Model, version 0.2.7" The Metropolis Project Team.