UCR CS220:
Synthesis of Digital Systems
Course
Information Lecture Topics Homework Individual Projects/Presentation
CS220 covers the synthesis and simulation of
digital systems. Topics include synthesis at the system, behavioral,
register-transfer, and logic levels; application-specific processors;
simulation; and emerging system-on-a-chip design methodologies.
Course information
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Instructor |
Harry Hsieh, (harry@cs.ucr.edu),
Engineering Unit II, Room 339 Office hours: Tue Wed 11:00am-Noon, or by appointment |
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Class meeting |
Engineering Unit II, Room 315, TR 9:40AM-11AM |
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Textbooks |
Recommanded: Additional reading will be distributed throughout the quarter. |
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Prerequisite |
CS/EE120B(Digital systems), CS141, CS161, and consent of instructor |
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Call # and units |
33037, 4 units. |
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Grade |
Examinations 60%, Research Project / Research Review 25%, Homework 15% There are two options a student may choose: a Research Project option, or a Research Review option. Project topic, or review option must be chosen by the third week of the class (Tue, 10/11). Research project involves an individual research work carried out throughout the quarter. Weekly meeting will be held to make sure sufficient progress were made. Two presentations and a final project report are required. A "progress" presentation will be given by the student to introduce to the class the research work , and a final project presentation will serve to conclude the project. The idea is that the result of the project, possibly with one more quarter of independent study, will have enough technical content for a conference or workshop publication. Research review option involves presentation of two different research papers. Reviewers may need to go beyond the paper to understand the material and be able to answer questions from the audience. A final summary/critique of the papers will be turned in at the end of the quarter. Letter grades are assigned according to the usual 85/70/60/50 rule: 85% and above correspond to an A, 70% and above to a B, 60% and above to a C, 50% and above to a D, and less than 50% to an F. +/- grades will be given. Curving may be done on individual items only if it helps the class. You are NOT competing against one another -- you can all earn A's (and that has happened in the past), so work together and help each other to succeed. |
Lecture
Topics (schedule are tentative and subject to change)
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Date |
Topic |
Corresponding |
Lecture notes |
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Th 9/29 |
Introduction to microelectronics and synthesis |
De Micheli, chapter 1 |
pdf_6 pdf_2 |
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Tu 10/4 |
Hardware Modeling |
De Micheli, chapter 1, 3 |
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Th 10/6 |
Architectural Synthesis |
De Micheli, chapter 3, 4 |
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Tu 10/11 |
Scheduling Algorithm |
De Micheli, chapter 5 |
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Th 10/13 |
Scheduling Algorithm, Resource Sharing, and Binding |
De Micheli, chapter 5, 6 |
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Tu 10/18 |
Two-Level Combinational Logic Optimization |
De Micheli, chapter 7 |
pdf_6 pdf_2 |
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Th 10/20 |
Two-Level Combinational Logic Optimization |
De Micheli, chapter 7 |
pdf_6 pdf_2 |
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Tu 10/25 |
Two-Level Combinational Logic Optimization |
De Micheli, chapter 7 |
pdf_6 pdf_2 |
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Th 10/27 |
Midterm Review |
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Tu 11/1 |
Midterm Examination |
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Algorithm_2 |
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Th 11/3 |
Lecture postponed, work on your presentation/project! |
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Tu 11/8 |
Student Presentation #1a |
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Th 11/10 |
Student Presentation #1b |
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Tu 11/15 |
Two-Level Combinational Logic Optimization |
De Micheli, chapter 7 |
pdf_6 pdf_2 |
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Th 11/17 |
Multi-Level Combinational Logic Optimization |
De Micheli, chapter 8 |
pdf_6 pdf_2 |
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Tu 11/22 |
Lecture postponed, work on your project! |
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Th 11/24 |
Happy Thanksgiving. Lecture cancelled. |
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Tu 11/29 |
Multi-Level Combinational Logic Optimization |
De Micheli, chapter 8 |
pdf_6 pdf_2 |
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Th 12/1 |
Sequential Logic Optimization, Cell-Library Binding |
De Micheli, 9, 10 |
pdf_6 pdf_2 |
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Tu 12/6 |
Student Presentation #2b |
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Th 12/8 |
Midterm Examination #2 |
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Algorithm_2 |
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Homeworks
- Homework 1 Due 10/18, 9:30AM, electronically
- Homework 2 Due 10/25, 9:30AM, electronically
- Homework 3 Due 11/29, 9:30AM, electronically
- Homework 4 Due 12/6, 9:30AM, electronically
Individual
Projects/Reviews
Sample Articles: (not yet finalized)
From IEEE transactions on Computer Aided
Design of Integerated Circuit and Systems, 2005:
Issue 10:
Quasi-Static Scheduling of Independent
Tasks for Reactive Systems
Cortadella, J.; Kondratyev, A.; Lavagno, L.; Passerone, C.; Watanabe, Y.
Intra-Task Voltage Scheduling on
DVS-Enabled Hard Real-Time Systems
Shin, D.; Kim, J.
Resource Allocation for Coarse-Grain FPGA
Development
Eguro, K.;
Issue 8:
Fine-grained transaction-level
verification: using a variable transactor for improved coverage at the signal
level
Ara, K.; Suzuki, K.
Towards a heterogeneous simulation kernel
for system-level models: a SystemC kernel for synchronous data flow models
Patel, H.D.; Shukla, S.K.
Issue 7:
Area-optimal technology mapping for
field-programmable gate arrays based on lookup tables
Chowdhary, A.; Hayes, J.P.
Issue 2:
Cosynthesis of energy-efficient multimode
embedded systems with consideration of mode-execution probabilities
Schmitz, M.T.; Al-Hashimi, B.M.; Eles, P.
Issue 1:
Fine-grained dynamic voltage and frequency
scaling for precise energy and performance tradeoff based on the ratio of
off-chip access to on-chip computation times
Kihwan Choi; Soma, R.; Pedram, M.
Sample Projects: