CS 260.2 Reading List
Advanced Execution Systems for Reliable High-Performance Computing
Monitoring Program Execution
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Online vs Offline Dynamic Analysis (Vijay Nagarajan & Rajiv Gupta)
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(**) X. Zhang and R. Gupta,
``Whole Execution Traces and their Applications,''
ACM TACO, 2(3):301-334, Sept. 2005.
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(**) V. Nagarajan, D. Jeffrey, R. Gupta, and N. Gupta,
``ONTRAC: A System for Efficient ONline TRACing for Debugging,''
ICSM, pages 445-454, Paris, Sept. 2007.
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Dynamic Binary Translation Enabled Profiling
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N. Nethercote and J. Seward,
``Valgrind: A Framework for Heavyweight Dynamic Binary Instrumentation,''
PLDI, pages 89-100, 2007.
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V. Nagarajan, H-S. Kim, Y. Wu, and R. Gupta,
``Dynamic Information Flow Tracking on Multicores,''
INTERACT, Salt Lake City, Feb. 2008.
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J. Chung, M. Dalton, H. Kannan, and C. Kozyrakis,
``Thread-Safe Dynamic Binary Translaction using Transactional Memory,''
HPCA, Feb. 2008.
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Checkpointing/Logging & Replay (Chen Tian)
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(**) Y. Saito,
``Jockey: A User-Space Library For Record-Replay Debugging,''
AADEBUG, pages 69-76, 2005.
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(**) S. Tallam, C. Tian, X. Zhang, and R. Gupta,
``Enabling Tracing of Long-Running Multithreaded Programs via Dynamic Execution Reduction,''
ISSTA, July 2007.
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S. Narayanasamy, G. Pokam, and B. Calder,
``BugNet: Continuously Recording Program Execution for Determinitic
Replay Debugging,''
ISCA, pages 284-295, 2005.
Speculative Optimization and Parallelization
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Speculation I
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Neelakantam et al.,
``Hardware Atomicity for Reliable Software Speculation,''
ISCA, 2007.
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Bridges et al.,
``Revisiting the Sequential Programming Model for Multi-Core,''
MICRO, 2007.
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Douillet et al.,
``Software-Pipelining on Multi-Core Architectures,''
PACT, 2007.
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Speculation II (Min Feng)
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(**) C. Ding, X. Shen, K. Kelsey, C. Tice, R. Huang, and C. Zhang,
``Behavior-Oriented Parallelization,''
PLDI, 2007.
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(**) M. Kulkarni, K. Pingali, B. Walter, G. Ramanarayanan, K. Bala, and P. Chew,
``Optimistic Parallelism Requires Abstractions,''
PLDI, 2007.
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K. Morita, A. Morihata, K. Matsuzaki, Z. Hu, and M. Takeichi,
``Automatic Inversion Generates Divide-and-Conquer Parallel Programs,''
PLDI, 2007.
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K. Chen, S. Malik, and P. Patra,
``Runtime Validation of Memory Ordering Using Constraint Graph Checking,''
HPCA, 2008.
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Memory Locality (Jilong Kuang)
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M. Chu, R. Ravindran, and S. Mahlke,
``Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures,''
MICRO, 2007.
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M. Wegiel and C. Krintz,
``The Mapping Collector: Virtual Memory Support for Generational, Parallel, and Concurrent Compaction,''
ASPLOS, 2008.
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R. Bhargava, B. Serebrin, F. Spadini, and S. Manne,
``Accelerating Two-Dimensional Page Walks for Virtualized Systems,''
ASPLOS, 2008.
High-Performance Architectures
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Power-Performance Trade-offs in Multicores and Multiprocessors (Kishore Kumar)
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Andreas Merkel and Frank Bellosa,
``Balancing Power Consumption in Multiprocessor Systems,''
EUROSYS, April 2006.
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David Tam and Reza Azimi,
``Thread Clustering: Sharing-aware scheduling on SMP-CMP-SMT Multiprocessors,''
EUROSYS, March 2007.
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Multicores and Multiprocessors: Architectural Support (Roger Moussalli)
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Wenisch et al.,
``Mechanisms for Store-wait-free Multiprocessors,''
ISCA, 2007.
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Zhu et al.,
``Synchronization State Buffer: Supporting Efficient Fine-Grain Synchronization
on Many-Core Architectures,''
ISCA, 2007.
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Kumar et al.,
``Express Virtual Channels: Towards the Ideal Interconnection Fabric,''
ISCA, 2007.
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Parallel Applications / Specialized Architectures
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Shaw et al.,
``Anton, a Special-Purpose Machine for Molecular Dynamics Simulation,''
ISCA, 2007.
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Amin et al.,
``AquaCore: A Programmable Architecture for Microfluidics,''
ISCA, 2007.
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Hughes et al.,
``Physical Simulation for Animation and Visual Effects: Parallelization and
Characterization for Chip Multiprocessors,''
ISCA, 2007.
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Yeh et al.,
``ParallAX: An Architecture for Real-Time Physics,''
ISCA, 2007.
Surviving Failures
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Surviving Failures in Parallel Systems
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R. Gioiosa, J.C. Sancho, S. Jiang, F. Petrini, and K. Davis,
``Transparent Incremental Checkpointing at Kernel Level: A Foundation for Fault Tolerance
for Parallel Computers,''
ACM Supercomputing, 2005.
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G. Bronevetsky, D. Marques, K. Pingal, M. Schulz, and P. Szwed,
``Application-level Checkpointing for Shared Memory Programs,''
ASPLOS, 2004.
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S-E. Choi and S.J. Deitz,
``Compiler Support for Automatic Checkpointing,''
Intl Symp. on High Performance Computing Systems and Applications, 2002.
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Surviving Failures in Servers (Jessica Browdus)
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M.C. Rinard, C. Cadar, D. Dumitran, D.M. Roy, T. Leu, and W.S. Beebee,
``Enhancing Server Availability and Security Through Failure-Oblivious Computing,''
OSDI, pages 303-316, 2004.
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(**) F. Qin, J. Tucek, J. Sundaresan, and Y. Zhou,
``Rx: Treating Bugs as Allergies - A Safe Method to Survive Software Failures,''
SOSP, pages 235-248, 2005.
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B. Demsky and M.C. Rinard,
``Data Structure Repair Using Goal-directed Reasoning,''
ICSE, pages 176-185, 2005.
Security
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Information Flow Analysis (Yuling Li)
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G.E. Suh, J.W. Lee, D. Zhang, and S. Devadas,
``Secure Program Execution via Dynamic Information Flow Tracking,''
ASPLOS, pages 85-96, 2004.
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F. Qin, H. Chen, Z. Li, Y. Zhou, H-S. Kim, and Y. Wu,
``LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting
General security Attacks,''
MICRO, 2006.
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G. Venkataramani, I. Doudalis, Y. Solihin, M. Prvulovic,
``FlexiTaint: Programmable Architectural Support for Efficient Dynamic Taint Propagation.''
HPCA, 2008.
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OS and Architectural Support (Vaibhav Parulkar)
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D. Lie, C. Thekkath, M. Mitchell, P. Lincoln, D. Boneh, J. Mitchell, and M. Horowitz,
``Architectural Support for Copy and Tamper Resistant Software,''
ASPLOS, pages 168-177, November 2000.
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B. Rogers, C. Yan, S. Chhabra, M. Prvulovic, and Y. Solihin,
``Single-Level Integrity and Confidentiality Protection for Distributed Shared Memory Multiprocessors,''
HPCA, Feb. 2008.
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(**) X. Chen, T. Garfinkel, E.C. Lewis, P. Subrahmanyam, C.A. Waldspurger, D. Boneh, J. Dwoskin, D.R.K. Ports,
``Overshadow: A Virtualization-Based Approach to Retrofitting Protection in Commodity Operating Systems,''
ASPLOS, 2008.
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O. Mutlu and T. Moscibroda,
``Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors,''
MICRO, 2007.
Debugging Techniques
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Fault Location I (Rajiv Gupta)
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(**) N. Gupta, H. He, X. Zhang, and R. Gupta,
``Locating Faulty Code Using Failure-Inducing Chops,''
ASE, pages 263-272, Nov. 2005.
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(**) X. Zhang, N. Gupta, and R. Gupta
``Locating Faults Through Automated Predicate Switching,''
ICSE, pages 272-281, May 2006.
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(**) X. Zhang, N. Gupta, and R. Gupta
``Pruning Dynamic Slices With Confidence,''
PLDI, pages 169-180, 2006.
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Fault Location II (Dennis Jeffrey)
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(**) D. Jeffrey, N. Gupta, and R. Gupta,
``Fault Localization using Value Replacement,''
ISSTA, July 2008.
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(**) D. Jeffrey, N. Gupta, and R. Gupta,
``Uncovering the Root Cause of a Memory Bug,''
submitted.
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Fault Location III (Casey Czechowski)
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S. Hangal and M. S. Lam,
``Tracking Down Software Bugs using Automatic Anomaly Detection,''
ICSE, pages 291-301, May 2002.
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Y. Xie and D. Engler,
``Using Redundancies to Find Errors,''
FSE, pages 51-60, November 2002.
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(**) Pin Zhou, Wei Liu, Long Fei, Shan Lu, Feng Qin, Yuanyuan Zhou, Samuel Midkiff, Josep Torrellas,
``AccMon: Automatically Detecting Memory-related Bugs via Program Counter-based Invariants,''
MICRO, 2004.
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(**) S. Lu, P. Zhou, W. Liu, Y. Zhou, and J. Torellas,
``PathExpander: Architectural Support for Increasing the Path Coverage
of Dynamic Bug Detection,''
MICRO, 2006.
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Comparison Based Debugging (Dhrumil Shah)
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X. Zhang and R. Gupta,
``Matching Execution Histories of Program Versions,''
ESEC-FSE, pages 197-206, September 2005.
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V. Nagarajan, R. Gupta, X. Zhang, M. Madou, B. De Sutter, and K. De Bosschere,
``Matching Control Flow of Program Versions,''
ICSM, pages 84-93, Paris, September 2007.
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M.K. Ramanathan, A. Grama, and S. Jagannathan,
``Sieve: A Tool for Automatically Detecting Variations Across Program Versions,''
ASE, 2006.