University of Arizona Computer Science: Programming Languages and Compilers Research

Prior Funding

Integrating Dynamic Slicing into the cordbg Debugger
Phoenix/SSCLI, Microsoft Research, Redmond, Washington,
4/2006-3/2007 (PI: N. Gupta & Co-PI: R. Gupta)

Morphable Software Services: Self-Modifying Programs for Distributed
Embedded Systems
National Science Foundation, ITR Medium Grant Program,
CCF-0324969, 10/2003-9/2007 (PI: R. Gupta, with Georgia Tech)

Matching Execution Histories of Program Versions
IBM, Eclipse Innovation Award,
1/2005-12/2005 (PI: R. Gupta & Co-PI: N. Gupta)

Compiling for Processors with Fine-Grained Threading,
Heterogenous Cores, and Sophisticated Data Management
Intel Corporation, Microcomputer Research Lab, Santa Clara, CA,
9/2003-8/2006 (PI: R. Gupta)

Using Phoenix for Program Slicing and its Application to Defect Analysis
Microsoft Research, Redmond, Washington,
9/2003-8/2006 (PI: R. Gupta)

Information Encoding for Energy Efficient Processor Design
National Science Foundation, CISE, Computer Systems Architecture Program,
CCF-0208756, 9/2002-8/2006.

Code and Data Segment Optimizations for Mixed Width Instruction Set
Embedded Processor
National Science Foundation, CISE, ITR Small Grant Program,
CCF-0220334, 9/2002-8/2005.

Data Compression Techniques for Improving Memory Hierarchy Performance
National Science Foundation, CISE, Compiler Program,
CCF-0105355, 9/2001-8/2005.

Protecting Software Through Program Slicing and Obfuscation Transformations
IBM, Eclipse Innovation Award,
1/2003-12/2003.

Power-Adaptive Microarchitecture and Compiler Design for Mobile Computing
DARPA, Power Aware Computing/Communications Program,
Award no. F29601-00-1-0183, 7/2000-11/2002.

Exploiting Speculation and Predication for Branch and Load Optimizations
Intel Corporation, Microcomputer Research Lab, Santa Clara, CA,
9/1999-6/2002.

A Framework for Path and Resource Sensitive Optimizations
National Science Foundation, CISE, Compiler Program,
CCR-0096122, 9/1998-8/2002.

Experimental Evaluation of Scalable Optimization Techniques
National Science Foundation, EIA, Experimental Systems Program,
EIA-9806525, 9/1998-8/2002.

On-line Avoidance of Monitoring Intrusion in Distributed Systems
National Science Foundation, Operating Systems Program,
CCR-9996362/CCR-9704350, 6/1997-8/2000.

Comparative Debugging of Optimized Code
Hewlett Packard Laboratories, Chelmsford, Massachusetts,
1/1996-4/1998.

Demand Driven Computation of Partial Data Flow and its Application
in Software Engineering
National Science Foundation, Software Engineering Program,
CCR-9402226, 9/1995-8/1998.

Machine Dependent Analysis for Exploiting ILP in VLIW Architectures
Intel Corporation, Microcomputer Research Lab, Santa Clara, CA,
1/1995-12/1998.

Optimization Techniques for Superscalar and VLIW Architectures
Hewlett Packard Laboratories, Palo Alto, California,
3/1995-4/1998.

Loop Transformations and Scheduling Strategies for Parallelizing Software
National Science Foundation, Presidential Young Investigator Award,
CCR-9157371, 8/1991-12/1997.

	Integrating Dynamic Slicing into the cordbg Debugger Phoenix/SSCLI, Microsoft Research, Redmond, Washington, 4/2006-3/2007 (PI: N. Gupta & Co-PI: R. Gupta)
	Morphable Software Services: Self-Modifying Programs for Distributed Embedded Systems National Science Foundation, ITR Medium Grant Program, CCF-0324969, 10/2003-9/2007 (PI: R. Gupta, with Georgia Tech)
	Matching Execution Histories of Program Versions IBM, Eclipse Innovation Award, 1/2005-12/2005 (PI: R. Gupta & Co-PI: N. Gupta)
	Compiling for Processors with Fine-Grained Threading, Heterogenous Cores, and Sophisticated Data Management Intel Corporation, Microcomputer Research Lab, Santa Clara, CA, 9/2003-8/2006 (PI: R. Gupta)
	Using Phoenix for Program Slicing and its Application to Defect Analysis Microsoft Research, Redmond, Washington, 9/2003-8/2006 (PI: R. Gupta)
	Information Encoding for Energy Efficient Processor Design National Science Foundation, CISE, Computer Systems Architecture Program, CCF-0208756, 9/2002-8/2006.
	Code and Data Segment Optimizations for Mixed Width Instruction Set Embedded Processor National Science Foundation, CISE, ITR Small Grant Program, CCF-0220334, 9/2002-8/2005.
	Data Compression Techniques for Improving Memory Hierarchy Performance National Science Foundation, CISE, Compiler Program, CCF-0105355, 9/2001-8/2005.
	Protecting Software Through Program Slicing and Obfuscation Transformations IBM, Eclipse Innovation Award, 1/2003-12/2003.
	Power-Adaptive Microarchitecture and Compiler Design for Mobile Computing DARPA, Power Aware Computing/Communications Program, Award no. F29601-00-1-0183, 7/2000-11/2002.
	Exploiting Speculation and Predication for Branch and Load Optimizations Intel Corporation, Microcomputer Research Lab, Santa Clara, CA, 9/1999-6/2002.
	A Framework for Path and Resource Sensitive Optimizations National Science Foundation, CISE, Compiler Program, CCR-0096122, 9/1998-8/2002.
	Experimental Evaluation of Scalable Optimization Techniques National Science Foundation, EIA, Experimental Systems Program, EIA-9806525, 9/1998-8/2002.
	On-line Avoidance of Monitoring Intrusion in Distributed Systems National Science Foundation, Operating Systems Program, CCR-9996362/CCR-9704350, 6/1997-8/2000.
	Comparative Debugging of Optimized Code Hewlett Packard Laboratories, Chelmsford, Massachusetts, 1/1996-4/1998.
	Demand Driven Computation of Partial Data Flow and its Application in Software Engineering National Science Foundation, Software Engineering Program, CCR-9402226, 9/1995-8/1998.
	Machine Dependent Analysis for Exploiting ILP in VLIW Architectures Intel Corporation, Microcomputer Research Lab, Santa Clara, CA, 1/1995-12/1998.
	Optimization Techniques for Superscalar and VLIW Architectures Hewlett Packard Laboratories, Palo Alto, California, 3/1995-4/1998.
	Loop Transformations and Scheduling Strategies for Parallelizing Software National Science Foundation, Presidential Young Investigator Award, CCR-9157371, 8/1991-12/1997.