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Ordinary programs contain large amounts of instruction level parallelism and can keep busy processors with issue widths as high as 32 and 64 instructions per cycle. However, extracting such high levels of ILP requires examination of instructions over a large instruction window and the availability of a highly effective memory dependence prediction mechanism to guide load speculation.
In this talk I will present designs of superscalar and VLIW architectures that address the instruction window and memory dependence problems. The design of the direct wakeup superscalar microarchitecture which supports a practical implementation of a large instruction window and a highly accurate dependence prediction mechanism will be presented. A VLIW processor relies on the compiler to extract ILP over large instruction windows. However, due to the conservative nature of compile-time dependence analysis, the amounts of ILP that can be uncovered in general purpose code is limited. I will present the design of a VLIW processor that incorporates a load speculation mechanism based upon value prediction to overcome the performance barrier posed by memory dependences.