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Programs that manipulate data at subword level, i.e. bit sections within a word, are common place in the embedded domain. Examples of such applications include media processing as well as network processing codes. These applications spend significant amounts of time packing and unpacking narrow width data into memory words. These operations not only lead to increased instruction counts, they also make inefficient use of register resources. Since registers are capable of holding a full data word, when a subword variable is assigned a register, only part of the register is used.
In this talk I will present the Bit Section eXtension (BSX) to the ARM instruction set which allows direct manipulation of subword data which can be used to significantly reduce instruction counts. Since BSX allows direct referencing of bit sections within registers and therefore multiple subword variables can be made to simultaneously reside in the same register without hindering accesses to these variables. However, a new register allocation algorithm is needed that is aware of the bitwidths of program variables and is capable of packing multiple subword variables into a single register. I will describe one such algorithm which we have found to significantly reduce register requirements.