TRADEOFF ANALYSIS

Design #

 Team Size Cost Size Power Prototype Features Flexibility/ Usability Time-To-Prototype Time-To-Market
JPEG Decoder Avoided JPEG Decoder project.  Both members of our group are CS Majors and have not taken CS 120 B and/or CS122.
 

Configurable Logic Fabric (FPGA) design/simulator

 VHDL

 

 

 2 people group -

Prakash Chulani

Po Fung

 

We chose to  implement FPGA project using a two person group since we believe we can handle the work load and can easily work around each other  schedules. Also because we are trying to incorporate XP Programming for the development of our project.

 # Xilinx XS40 (8051, FPGA)

Breadboard

(Cost of hardware provided by UCR)

 Xilinx XS40 Board: 

6" x 2" x 1"

 XS40 board - 

9 VDC @ 300 mA

 The features of the Xilinx XS40 is that it supports all XC9500, XC4000 XL devices of the 84 pin package.

The Xilinx XS40 is a 8051 microcontrollor with 32Kbyte SRAM, 7 Segment LED Display, and very importantly I/O Access pins plugs that can plug directly into standard solderless breadboards

Hence this device has the feature of the fulfilling the design specification that has been provide by this project. It can satisfy the necessary conditions for a cycle-accurate simulation of I/O, switch matrices, configurable logic blocks, and interconnect.

 This product is effective for student projects because of the flexibility and usability of the product. Because of the development of the pins which run along the sides of the board, the Xilinx XS40 allows for easy prototyping and access to all the I/O pins of the programmable logic device. Also another functionality with adds to the usability and flexibility of the board is that other devices such as LEDS, diodes etc. can be easily connected. Using the Iterative model and XP Programming seems to be the ideal method for our group to develop our FPGA simulator. Our first prototype is due on week 5, our second protoype on week 7 and our final prototype on week 10. Hence since three prototypes are required it just seems logical to employ the iterative software engineering model integrated with XP Programming since using this we can continuously design, analysis, implement, test and debug our FPGA simulator throughout its development. Rather than having a fixed approach of the waterfall model.  Marketing research of the project will begin during the earlier development of the FPGA simulator, yet focus on the marketing aspect will not begin till after the development of the second prototype. Our marketing strategy will depend on primarily on the final presentation and final interview while presenting our FPGA. It will not only show the functionality that FPGA has by the 10 week but the reusability of FPGA simulator for future FPGA simulator designs. This will include possible extra functionality that can be added to our FPGA if needed in the future. Such examples can be a parallel development of the FPGA design using a C++ simulator integrated with a simple scalar. 
Triscend E5 (8051, FPGA)

Breadboard

(Cost of hardware provided by UCR)		 Triscend E5

Board:

(Size not provided)

 Triscend E5 - 

5 V @ 2.5 A

 The features of Triscend E5 board consist of one RS- 232 channels with connectors, LED display with limit resistors, 128 kByte Flash and SRAM 

This device too has the feature of fulfilling the design specification that has provided by this project. Currently, the Xilinx seems more applicable due to the availability of resource manuals on it on the web

 The flexibility and usability of the software is still to some degree unknown to us. From the information that has been gathered this flexibility depends on the coding of the software programmer and the language that has been used.