CS/EE120B Summer 2 2003

UNIVERSITY OF CALIFORNIA, RIVERSIDE
Department of Computer Science and Engineering
Department of Electrical Engineering
CS/EE120B - Introduction to Embedded Systems
Summer 2 2003

is available below

Schedule: Lecture: 7/28/03 - 8/30/03, MTWR 9:40 - 11:10AM, 2365 Sproul Hall.
Laboratory:

Section 1: MTWR, 11:30AM - 3:30PM, 173 Surge. TA: Fang Chen

Section 2: MTWR, 3:30PM - 7:30PM, 173 Surge. TA: Lan Ye

Textbook:

Logic and Computer Design Fundamentals, M. Mano and C. Kime, Prentice Hall, 2001, 2^nd Ed.

A VHDL Primer, J. Bhasker, Prentice Hall, 2000, 3^rd Ed.

Embedded System Design: A Unified Hardware/Software Approach, Frank Vahid and Tony Givargis, Wiley & Sons, 2001.

The 8051 Microcontroller, Stewart and Miao, Prentice Hall, 2nd Ed.

Instructor: Dr. Enoch Hwang. Office: BRNHL A259. e-mail: ehwang@cs.ucr.edu. Office hours: Right after class. More detail and updated information on the web at www.cs.ucr.edu/~ehwang.

Prerequisites: EE/CS120A.

Objective: To learn to design digital systems at the register and processor levels focusing on sequential logic circuits and emphasizing the use of modern CAD tools. To learn about embedded systems and how to interface with them.

Topics: (Numbers in parenthesis are Mano sections. Numbers in square brackets are Vahid sections. Numbers in curly brackets are Stewart sections.)

Sequential Logic. (4)

Latches. (4-2)

Flip-Flops. (4-3)
Finite-State Machine (FSM).

Analysis of sequential circuits: Excitation equations. Next-state equations & tables. State diagrams. (4-4).

Synthesis of sequential circuits: State minimization. State encoding. Choice of memory elements. (4-4 - 4-7)[2.3].
Sequential logic components. (5) [2.3]

Registers (5-2, 5-3), counters (5-4, 5-5), memory (6-2, 6-3, 6-4) [5.3, 5.5] , PAL (6-8), CPLD (6-9).
Register-transfer design (7) [2.4, 2.5]
FSM + Datapath.

FSM with datapath (FSMD).

Synthesis of FSMDs.

Optimization: Register sharing. Functional-unit sharing. Bus sharing. [2.6].
Peripherals [4].

LEDs {3.5}.

Switches and Keypad {3.2.4} [4.6].

LCDs: L1682 (pinouts) [4.5].

Timers and counters [4.2].

Real-time clocks: MM58167 and 58321 [4.9]{3.11.2}.

UART [4.3].

Pulse width modulators [4.4]{3.12.2}.

A/D, D/A converters [4.8]{3.12}.

Interfacing microcontrollers [6].

8051 {2.1 - 2.9}, Z80, EZ80

Addressing: Memories [5.4] {2.4}, I/O ports [6.3]{2.6}, Interrupts [6.4] {2.9}.

LEDs {3.5}, LCD [4.5], Keypad [4.6] {3.2.4}.

Real-time clocks [4.9] {3.11.2}, UART [4.3], A/D, D/A converters [4.8] {3.12}.

Protocols [6] USB.

Tests: Two midterms: Wed Aug 6 and Tue Aug 19. Final: Friday August 29, 2003, 10:00AM - 12:00PM.

Academic dishonesty: It is your responsibility to be familiar with UCR's and the department's policies on academic dishonesty. See policy. Cheating will be punished severely.

Grading: Homeworks 10%, Labs 30%, 2 Midterms @ 15% each, Final 30%. You must get at least 50% or the class average on the test (whichever is smaller) on two of the three tests to pass the course.

Grades:

Grades. If you do not want your grades to be posted on-line, please email me to let me know. Otherwise, I will take your inaction to mean that you have given me the approval to post your grades on-line.

Homeworks:

Solutions:

Labs:

XS40 breadboard schematic

Draft versions of upcoming labs are found below

Lab 1: Storage component design using behavioral VHDL.
Lab 2: Datapath design using structural VHDL
Lab 3: FSM design of a 4-bit counter using behavioral VHDL.
Lab 4: FSMD design of a greatest common divisor calculator using behavioral VHDL.
Lab 5: FSM + D design of a greatest common divisor calculator using behavioral and structural VHDL.
Lab 6: FSM + D design of a microprocessor using behavioral and structural VHDL.
Lab 7: Interfacing the 8051 to 7-segment displays
Lab 8: Interfacing the 8051 to a keypad and 7-segment display

Lab Guidelines:

You should plan to stay for the duration of your 4-hour scheduled lab time. Labs are all posted on the web, so if you finish before a due date, you should proceed to work on the next lab. If it appears that students are leaving early, then measures may be taken.
Each lab assignment's grade will typically consist of your lab demo (simulation and board), and your lab report (writeup, source code and results).
No late lab submissions will be accepted.
Lab reports are due before the end of your scheduled lab time on the date you are checked off for your demo. Use the report form above. We will be using electronic turnin (see below).
The TA's will not be available for help 15 minutes before the end of each lab. This time is reserved for checking out completed labs.
The students are required to work in groups of two. Students are welcome to choose their own lab partners.
The TA's will check out the Xilinx boards to each group when required. Boards are only available during scheduled lab. Student must check the boards back in when done, and must be sure to sign the check in sheet. Students should also be sure the TA records your score your lab demo.
The Xilinx boards are pre wired. Please do not change any wiring unless specifically instructed by the TA.
You are required to go to the lab section you are registered in. If you wish to change your lab section, this must be pre-approved by the LECTURE TA.
The TA's and Lab Assistants will be there to assist you in any problems that you might face for the full four hours (except during the check off time). Please feel free to approach any of them with any problems or questions that you might have. If you have any problems or questions please email cs120b-t@cs.ucr.edu. One of the TA's will answer your question as soon as possible.
Any suggestions to help us improve the lab will be welcomed.