UCR EE/CS120B: Digital Systems


Lab 2: ALU design

I. Introduction

In this lab you are basically building a 2-bit ALU. You are required to write a behavioral description of an ALU. Note: when constructing the ALU, do not use LE's, AE's, and FA's as shown in the book. All you really need are case statements, etc ... The ALU should take in two 2-bit numbers have the following functionality:

The output of the ALU will consist of one 2-bit result and a carry/borrow bit. You are also required to write a testbench for this design. You will have to feed values into your design and demonstrate that it is correct. In order for certain elements to function correctly, (i.e. wait statements and internal signal tracing) you may be required to use Active-VHDL.

II. Active VHDL

  1. Run Active VHDL by clicking on the icon on the desktop. If a window pops up regarding evaluation terms, click on "I Agree"
  2. Create a new design and store in in C:\temp (don't forget to move it to your account and remove it from the temp directory when you are finished).
  3. Select "Add existing resource files" if you have already typed up your vhdl, otherwise select "Create new source files now"
  4. Once you have gotten you files loaded and compiled into Active VHDL, select Simulation->Initialize Simulation.
  5. Click on the small button next to the save icon to create a new waveform.
  6. Select "Waveform->Add Signals" and add all the signals in your testbench.
  7. Push the "Run" button and see if the output is what you hoped it would be.

III. Download VHDL

After you have verified the results using ALDEC, check out an XS40 board from the T.A. and download your code. You will need to use the decoder you previously designed to display the result of your ALU in decimal form on the 7-segment display present on the XS40 board. Verify the results.