UCR EE/CS 120A: Logic Design
Summer 1 2004
Lecture
Schedule Lab
Schedule Grades
Previous course offerings
Prereq: CS 61 Follow-up class: EE/CS 120B
EE/CS120A introduces you to the exciting world of digital design. Digital
circuits not only form the foundation of computers, but make possible many of
the advances around us, like cell phones, video games, medical instruments,
automotive systems, satellites, PDAs, music equipment, military equipment, store
automation. You name it -- if it runs on electricity, it's probably got digital
circuits (known as embedded systems) inside! 120A gets you up to speed on the
basics; the follow-up course, 120B, teaches you to build a computer, and to
build complete working embedded computing systems. EE/CS 120A and 120B are
taught jointly by the EE and CS&E departments.
Catalog
description :
EE/CS 120A. Logic Design (5) Lecture, 3 hours; laboratory, 6 hours.
Prerequisite(s): CS 061. Design of digital systems. Topics include Boolean
algebra; combinational and sequential logic design; design and use of
arithmetic-logic units, carry-lookahead adders, multiplexors, decoders,
comparators, multipliers, flip-flops, registers, and simple memories;
state-machine design; and basic register-transfer level design. Laboratories
involve use of hardware description languages, synthesis tools, programmable
logic, and significant hardware prototyping. Cross-listed with CS/EE 120A
Instructor(s) :
Enoch Hwang, Ph.D. (ehwang@cs.ucr.edu). Office hours: MTWR
9:30am-10:00am Office: Bourns Hall
A-259.
Lecture:
Section 001: MTWR 8:10am-9:30am Sproul Hall
2355
Labs:
Section 1: MTWR 10:00am-1:00pm BRNHL
B252
Section 2: MTWR 3:00pm-6:00pm BRNHL
B252
Teaching Assistants:
TA office hours:
Section 1: Shawn Nematbakhsh (snematbakhsh@cs.ucr.edu): Time: tba in
BRNHL
A-216
Section 2: Wei Wu (wwu@cs.ucr.edu):
Time: tba in BRNHL
B-252
Textbook:
Logic
and Computer Design Fundamentals and Xilinx Student Edition 4.2 Package, 3/E
, by Mano and Kime, 3rd edition
Course
grading:
The course consists of 100 points:
- Lecture component (65 points)
- 20 pts: Midterm
- 24 pts: Final
- 8 pts: Quizzes -- 4 @ 2 pts
- 8 pts: Homeworks -- 4 @ 2 pts
- 5 pts: In-lecture exercises
- Lab component (35 points)
- 30 pts: Lab assignments
- 5 pts: In-lab practical exam(s)
Grades will be
assigned using a conventional grading scale: 100-90 A, 89-80 B, 79-70 C, 69-60
D, 59-0 F. +/- grades will be given. Students are NOT competing against one
another, but rather against the scale -- all students can get good grades if all
do well. We may adjust ("curve") an individual assessment item if such adjusting
HELPS the class.
Minimum competency requirement: We want students to
master both the conceptual as well as the hands-on aspects of the course. Thus,
students must receive a passing grade (60% or better) in each of the
lecture component and lab component, in order to receive a passing course grade
(D- or better).
Study groups:
Study
groups - suggest going to the Science Library to meet and study there.
Class web site:
http://www.ilearn.ucr.edu/
Enrolling in
this course gives you automatic access to the UCR "ilearn" site Your login id is
the name field of your ucr student email address (name@student,ucr,edu), and
your initial password is your Student ID (no dashes or spaces).
Class email list:
CS/EE 120A mailing
List (send mail now or access the archive):
Most students will be automatically subscribed to this mailing list when
enrolled in the course. However, it is up to you to ensure that you are in fact
subscribed (you can go to the links above to check the subscription list).
Subject to change as the quarter progresses.
Read the book
before lecture! Reading ahead is one of the most effective ways of doing better
in class -- you'll be amazed how much more useful the lectures will be. We'll
follow the book closely.
- Week 1:
- M Ch1 -- Digital computers and information
- In-class
exercise 1
- T Ch2.1-2.4 -- Combinational logic circuits (gates, standard forms,
two-level optim., maps)
- Homework
1 solutions
- W Ch2.5-2.10 -- Combinational logic circuits (cover lightly)
(multi-level, other gates, xor, misc.)
- R Ch3.1-3.7 -- Combinational logic design (design concepts, space,
procedure, tech. mapping, verification, prog. logic)
- Quiz 1 solutions
- Week 2:
- M Ch4.1-4.4 -- Combinational functions and circuits (ckts, rudim. fcts.,
decoding, encoding)
- T Ch4.5-4.6 -- (selecting, comb. fct. imp. -- skip w/ dcd or mux) (SKIP
4.7-4.8 HDLs)
- Homework
2 solutions
- W Ch5.1-5.2 -- Arithmetic functions and circuits (iterative ckts,
adders, CLA)
- R Ch5.3-5.4 -- (subtraction, ALU,
multiplication)
- Quiz 2 solutions
- Week 3:
- M Ch5.6 -- (other arith. fcts, cover lightly, SKIP 5.7-5.8 HDLs)
- Review
- T MIDTERM Tue July 6 solutions
- W Ch6.1-6.3 -- Sequential circuits (defn, latches, flip-flops -- focus
in on D)
- R Ch6.4 -- Analysis with D flip-flops
- Homework
3 solutions
- Week 4:
- M Ch6.5 -- Design with D flip-flops (SKIP 6.6 -6.8)
- T Ch7.1-7.3 -- Register transfers (SKIP 7.4)
- Quiz 3 solutions
- W Ch7.5-7.6 (micro-ops)
- R Ch7.7-7.9 (register cell design, mux/bus transfers, serial)
- Homework
4 solutions
- Week 5:
- M HDLs
- T HDLs
- Quiz 4 solutions
- W Miscellaneous
- R Review
- FINAL:
Subject to change as the quarter progresses.
Read the lab
overview and report format.
- Material covered: You'll be responsible for learning material
covered in lecture, in the textbook, and in lab. We expect you to read the
textbook; lecture only emphasizes key material, but does not cover all
required material alone.
- Collaboration policy (TA/instructor may override for particular
assignment):
- Midterm, final, quizzes, lab practical -- Obviously no collaboration
- In-lecture exercises -- Dependent on instructor instructions for
particular exercise.
- Homeworks -- Collaboration strongly ENCOURAGED. Study groups are great.
You should still do your own solution, and should not turn in *identical*
solutions as others, but similar solutions are O.K. Remember though -- these
are designed to help you on the assesment items, so relying too heavily on
others will hurt you during assessment.
- Lab assignments -- Limited collaboration may be acceptable, but
submissions must represent YOUR OWN original work. Sharing code or
team-coding are not allowed. Copying code from ANY source (any book, current
or past students, past solutions, etc.) is not allowed. Collaboration may
consist of discussing the general approach to solving the problem, but
should not involve communicating in code or even pseudo-code. Students may
help others find bugs. Your code must be unique -- the odds of randomly
obtained highly-similar code is very low. Design, like surgery or driving a
car or playing golf, can only be learned by doing it yourself!
- Academic dishonesty: cheating is strongly punished. Report cheating
(anonymously if you wish) at: https://www.cs.ucr.edu/cheating/.
Note: In some courses, we use a powerful commercial tool that automatically
compares all programs (this quarter and from past quarters too), neglecting
changes in variable names, spacing, etc., and detects copied code. We
regularly catch several cases of copying in this course EVERY QUARTER. PLEASE,
don't risk it!! A couple more notes. Be aware that a subset of exams may be
photocopied, for comparison with exams submitted for regrades. Also, be aware
that lying to an instructor in order to be able to make up a missed exam or in
other ways to obtain a better grade can be treated as academic dishonesty.
During exams, cell phones must be stored away in a place not visible (e.g.,
inside a backpack).
- Regrade policy: regrade requests must be submitted in writing
and within one week of the distribution of the graded material.
Grade-database errors should also be pointed out within one week of posting.
- Communicating with the instructors and TAs: when sending electronic
mail to the instructors or TAs, please remember that many students have the
same name, and your instructor may be teaching other courses too. So please
give your full name and list the course you are referring to, and preferably
include your student ID number. We prefer that you use your UCR email account
so that you get used to it (remember that UCR sends many official notices now
only by email). Please try to be polite and professional, and use reasonable
grammar and formatting.
- Cell phones: During lectures and lab sessions, please turn off your
cell phone.
- Lab attendance: is required for the full 3-hour lab. If you finish
early, work ahead on labs, do homework, read ahead, and help others if allowed
(teaching increases your own learning).
- Lab enrollment : To reduce disruptions and provide for the best
educational environment, all persons in lab during scheduled lab time should
be formally registered in that section. In general, no swapping sections and
no unregistered people in the lab are allowed, even if there are extra
computers.
- Homeworks and lab reports: Homeworks are due at the
beginning of the class period on the due date. Lab reports are due at the
beginning of the lab period on the due date. No late homeworks are accepted.
Your work must be completely typeset with a word processor. Circuit diagrams
can be drawn using any drawing program or by hand, but it must be very neat.
Handwritten works will NOT be accepted. Lab reports must follow this
format.
- Late/early policy for lab assignments:
- Late penalty for lab assignments due before the midterm: 7% for 1-day
late, 14% for 2-days, not accepted thereafter.
- Late penalty for lab assignments due after the midterm: 10% for 1-day
late, 20% for 2-days, not accepted thereafter.
- BONUS for any lab assignment turned in EARLY: 2% for 1-day early, 4% for
2-days early, 6% for 3-days or more early.
- "Day early/late" is defined as 24 hours before/after the due time.
- Time Requirements: This is a five-unit engineering course. As such,
you should expect to spend 3 hours/week in lecture, 6 hours/week in lab, and
6 to 10 hours/week doing individual study (readings, homeworks,
programming, lab preparation, etc) -- no exaggerating here! Please don't
underestimate the time you will need to spend on this course. These are real
time amounts spent by successful past students. Engineering and CS are
challenging disciplines requiring extensive time to master -- it's worth it in
the end (great jobs, great pay, respect, etc.), but those things don't come
for free. So practice, practice, practice! Work hard in school, then reap the
rewards of a great career.
- Final grades: Per university policy, changes to your final grade
will be made only in the event of a clerical error. Asking your
instructor how far you were from a cutoff and what extra work you can do to
improve the grade is not appropriate.