UNIVERSITY OF CALIFORNIA, RIVERSIDE
Department of Computer Science
Department of Electrical Engineering
EE/CS120A - Logic Design
Winter 2001

Schedule: Lecture: 1/4/01 - 3/24/01, TR, 8:10 - 9:30AM, STAT B650.

Laboratory:

Section 021: MW, 3:10 - 6:00PM, BRNHL B144
Section 022: TR, 2:10 - 5:00PM, BRNHL B144
Section 023: MF, 8:10 - 11:00AM, BRNHL B144

Textbook: Digital Design Principles & Practices, J. Wakerly, Prentice Hall, 2001, 3rd Ed.
Optional: A VHDL Primer, J. Bhasker, Prentice Hall, 2000, 3rd Ed.

Instructor: Dr. Enoch Hwang. Office: BRNHL A303. e-mail: ehwang@cs.ucr.edu or ehwang@ee.ucr.edu. Office hours: TR 11:10 - 12:30 or until no more students, which ever comes first. More detail and updated information on the web at www.cs.ucr.edu/~ehwang.

Prerequisites:

Objective: To learn the principles of digital logic design focusing on combinational logic circuits.

Topics:

  1. Introduction. Digital devices. Integrated circuits (IC). Digital-design levels. CAD tools.

  2. Number systems, conversions, arithmetic in binary, negative numbers (2).

  3. Boolean Algebra and Logic Design.

    4. Basic theorems, boolean functions (4.1), minterms & maxterms, canonical and standard forms (4.1.6).
    Technology mapping

  4. Simplification of Boolean Functions.

    5. n-cubes, Karnaugh maps, simplifying expressions (4.3.4).
    "don't-care" (4.3.7).
    Quine-McCluskey (tabulation) method (4.4).

  5. Combinatorial Components.

    6. decoders (5.4),
    encoders (5.5),
    three-state devices (5.6),
    multiplexers (mux) (5.7),
    comparators (5.9),
    adder/subtractor (5.10),
    ROM (10.1, 10.1.1),
    PLA (5.3),
    ALU (5.10).

  6. VHDL (4.7)

  7. Miscellaneous

    8. Hamming Codes (2.15.3),
    Hazard-Free Design,
    Gate Implementations (3) - logic levels, noise margins, fan-in/out, logic gate families, CMOS gates, VLSI Technology.
    Transistors on a chip as seen through an electron microscope.

  8. Sequential Logic

    9. latches, flip-flops (7.2).

Holidays: 1/15/01, 2/19/01.

Tests: Two midterms: Thu. Feb. 1 and Thu. Feb. 22. Final: Thursday March 22, 2001, 3:00PM - 6:00PM.

Grading: Homeworks 10%, Labs 30%, 2 Midterms @ 15% each, Final 30%. Must get at least 50% on two of the three tests to pass course.

Grades:

Homeworks:

Solutions:

Labs:

VHDL links:

  • Summary of VHDL commands
  • Complete VHDL reference guide.
  • VHDL Lab examples
  • Online VHDL tutorial
  • Online VHDL textbook: VHDL Cookbook
  • VHDL synthesis tutorial
  • Simple VHDL examples
  • Free Peak VHDL simulator and synthesizer
  • $45 Aldec VHDL simulator and synthesizer student edition
    •

    Other related links:

  • 74xx Datasheets
  • Complete IC Datasheets
  • Online VLSI Design Tutorial
  • History of the transistor
  • Free Acrobat reader
    •