University of California, Riverside
Department of Electrical Engineering
EE/CS120A - Logic Design
Winter 2000

Schedule: Lecture: 1/7/00 - 3/17/00, MWF, 2:10 - 3:00P, BRNHL A125.

Laboratory:

Section 021: MW, 3:10 - 6:00P, BRNHL B144
Section 022: TR, 2:10 - 5:00P, BRNHL B144
Section 023: TR, 6:10 - 9:00P, BRNHL B144
Section 024: MF, 11:10 - 2:00P, BRNHL B144

Textbook: Principles of Digital Design, D. Gajski, Prentice Hall, 1997.

Instructor: Dr. Enoch Hwang. Office: BRNHL A377. e-mail: ehwang@cs.ucr.edu. Office hours: MW, 1:00P - 2:00P or by appointments.

Prerequisites: CS 10.

Topics:

  1. Introduction. Design Representation. Levels of Abstractions. Design Process. CAD Tools.

  2. Data Types and Representation. Binary numbers.

  3. Boolean Algebra and Logic Design. Minterms & Maxterms

  4. Simplification of Boolean Functions.

  5. Combinatorial Components.

  6. Sequential Logic. Flip-Flops

Holidays: 1/17 and 2/21.

Tests: Two midterms: Mon 1/31 and Fri 2/25. Final: Saturday March 25, 2000, 11:30A -2:30P.

Midterm 1 solutions Midterm 1 statistics Homework 2 solutions Midterm 2 solutions Homework 3 solutions
Final lab project Finals solutions

Grading: Homeworks 10%, Labs 20%, 2 Midterms @ 20% each, Final 30%.

VHDL links:
  • Online VHDL tutorial
  • Online VHDL textbook: VHDL Cookbook
  • VHDL synthesis tutorial
  • Simple VHDL examples
    •  Other related links:
  • IC Datasheets
  • Online VLSI Design Tutorial
  • History of the transistor
    •