SYLLABUS FOR ARCHITECTURE SECTION OF THE COMPUTER SYSTEMS EXAM
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Fundamentals of computer design
	The task of a computer designer
	Technology and computer usage trends
	measuring and reporting performance
	Principles of computer design
	Concept of memory hierarchy

Instruction set design
	Classifying instruction set architectures
	memory addressing
	Operations in the instruction set
	Type and size of operands
	Encoding an instruction set
	The role of compilers

The processor: Datapath and Control
	Building a datapath
	Single cycle implementation
	Multiple cycle implementation
	Microprogramming: Symplifying control design
	Exceptions

Pipelining
	What is pipelining?
	Pipeline hazards
	Data hazards
	Control Hazards
	Evaluating pipelined processor performance
	Design of a pipelined processor
	Branches
	  Branch elimination
	  Delayed branch
	  Branch prediction
	  Branch target capture
	Interlocks
	  Forwarding/bypassing
	  Address generation interlocks
	  Execution interlocks
	Current trends

Cache memory
	Basic notions
	Cache structure
	Writing to the cache
	Replacement algorithms
	Other types of caches:
	  Split I- and D-caches
	  On-chip caches
	  Multi-level caches
	  Write assembly caches
	Cache analysis
	Cache design considerations
	Virtual-to-real translation
	  Translation lookaside buffer (TLB)
	  Overlapping V --> R translation

Memory-hierarchy design
	Principle of locality
	Caches
	Main memory
	Virtual memory
	  Virtual-memory structure
	  Virtual-memory mapping
	  Improving program locality
	Protection of virtual memory
	Design of memory hierarchy

Interfacing processors and peripherals
	Types and characteristics of i/o devices
	i/o buses
	i/o interfaces to the memory, processor, and OS
	i/o performance measures

Concurrent processors
	Vector processors
	  Compiler vectorization 
	  Enhancing vector performance
	Interleaved memory
	Multiple-issue processors:
	  Superscalar
	  VLIW
	Instruction-level parallelism (ILP)
	Instruction scheduling
	Compiler support for exploiting ILP

Interconnection networks
	Perfect shuffle
	Shuffle-exchange interconnection
	Multistage networks
	
Multiprocessors
	Multiprocessor architectures
	The cache coherence problem
	  Sources of the problem
	  Consistency models
	  Two protocol approaches:
	     Snoopy protocols
	     Directory-based protocols
	Synchronization Techniques
	The remote load problem
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REFERENCES:

1.  David A. Patterson and John L. Hennessy: 
    Computer Organization & Design: The Hardware/Software Interface,
    Morgan Kaufmann, 1994.

2.  David A. Patterson and John L. Hennessy: 
    Computer Architecture, A Quantative Approach,
    2nd Ed., Morgan Kaufmann, 1996.

3.  Michael J. Flynn: Computer Architecture, pipelined and parallel
    processor design, Jones and Bartlett, 1995.

4.  Harold S. Stone: High-Performance Computer Architecture, 3rd Ed.,
    Addison Wesley, 1993.  

5.  Mike Johnson: Superscalar microprocessor design,
    Prentice Hall, 1990.
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