--Demand pacemaker state machine

--Created by:
--Eric Frohnhoefer

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity FSM is
  
  port ( clk : in std_logic;                           -- clock
         reset : in std_logic;                         -- reset bit
         event : in std_logic;                         -- event input
         event_clear : out std_logic;                  -- clear event
         watch_dog : in std_logic_vector(16 downto 0); -- watch dog timer
         watch_dog_reset : out std_logic;              -- reset the watch dog timer
         timer1 : in std_logic_vector(16 downto 0);    -- timer 1
         timer1_reset : out std_logic);                -- timer 1 reset

end FSM;

architecture FSM_arch of FSM is

  type STATE_TYPE is (reset, reset2, Rdetect, Rdetect2,wait_state , Rdetect3, pulse, pulse2); -- states
  signal state : STATE_TYPE;
  
begin  -- FSM_arch
  state_machine : process (reset, clk)
  begin  -- process
    if (reset ='1') then
      state <= reset;
    elsif (clk'event and clk='1') then
      case state is
        
-------------------------------------------------
        --reset state
-------------------------------------------------
        when  reset =>
          watch_dog_reset <= '1';
          state <= reset2;
        when reset2 =>
          watch_dog_reset <= '0';
          state <= Rdetect;
-------------------------------------------------
        --Detect first R-wave
-------------------------------------------------
        when Rdetect =>
          if (event='1') then
            event_clear <= '1';
            timer1_reset <= '1';
            state <= Rdetect2;
          elsif (event = '0')
            state <= Rdetect
          end if;
        when Rdetect2 =>
          event_clear <= '0';
          timer1_reset <= '0';
          state <= wait_state;
-------------------------------------------------
        --Wait for timer to expire
-------------------------------------------------
        when wait_state =>
          if (timer1 = "0000000000000000") then
            state <= pluse;
          elsif (timer > "0000000000000000")
            state <= Rdetect2;
          end if;
-------------------------------------------------
        --Detect second R-wave
-------------------------------------------------
        when Rdetect3 =>
          if event = '1' then
            state <= Rdetect;
          elsif (event ='0')
            state <= wait_state;         
          end if;
-------------------------------------------------
        --pulse state
-------------------------------------------------
        when pulse =>
          pulse <= '1';
          state <= pulse2;
        when pulse2 =>
          pulse <= '0';
          state <=Rdetect

        when others => null;
      end case;
    end if;
  end process;
end FSM_arch;