CS203A Advanced Computer Architecture
2005 Fall
Instructor: Laxmi Bhuyan
Classpage: CS203A

               
In this report, we are going to run some tests on the impact of instruction level parallelism and cache on the overall performance of the CPU. We find that the CPU performance is getting better with the increase of cache size. And this tendency holds true for the respective parameters that contribute to the overall alternation of the cache size. The result in this report is helpful to design a CPU with higher performance.

              

Attempting to decrease the Cycles per Instruction (CPI) of an out-of-order execution we implemented a victim buffer into the Simplesim simulator. This change should affect the miss penalty and thus the CPI. We introduce two different kinds of victim buffers. The difference lies in the way it interacts with the Instruction Cache Level 1 (IL1) and the way it gives the required data to the CPU. Simulations show a speedup in performance for both victim buffer models. The result in this report is helpful to design a CPU with higher performance.