Internal Capacitance of "reference design"

In the past, gate delay was the dominating factor in circuit design. However as the feature size of VLSI devices continues to decrease, interconnect delay becomes inceasingly important. Interconnect delay has become dominating factor in determining system performance. In many systems designed today, as much as 50% to 70% of cycle are consumed by interconnect delay. The interconnect delay is result of interconnect( or routing) capacitance.

Routing capacitance is dependent on interconnect(routing wire) sizing and spacing between them. It is the total of area capacitance, fringing capacitance and coupling capacitance as shown in figure 1. Area capacitance and fringing capacitance is mainly dependent on the wire size and coupling capacitance is mainly dependent on the spacing between the wires. The optimal wire sizing and spacing is a hot topic for current research. Diffrent works showed that significant delay reduction can be achieved by optimal wire-sizing in submicron design. However no explicite work found on coupling capacitance. As VLSI technology continues to push toward deep submicron, the coupling capacitance between adjacent wires has become the dominating component in the total routing capacitance due to the decreasing spacing between adjacent wires for submicron processes. There is a question whether an optimal wire-sizing solution which considers only the area and fringing capacitances would remain optimal when the coupling capacitance is considerd. High coupling capacitance in deep submicron design results in both noise and additional delay.

By increasing the spacing between adjcent conductors its obvious that the coupling capacitance is decreasing.We have compared the coupling capacitance for different bus size considering the bus size decrease and spacing increase by same factor.We use two formulas to find this capacitance.

The first one is simple with assumpltions like one ground plane, no effect of wire size and fringing fields on coupling capacitance and thickness of wire and dielectric are same.

C1=e*T/S

e=permitivity of dielectric

T=thickness of conductor

S=spacing between adjcent conductors

The second formula is from a VLSI design book with considering one ground palne and assuming no effect of wire width on coupling capacitance.

C2=e*1.064(T/S)*((T+2H)/(T+2H+0.5S)^0.695

e=permitivity of dielectric

T=thickness of conductor

S=spacing between adjcent conductors

H=thickness of dielectric

The folllowing table summarized the C1/e and C2/e which is normalised coupling capacitance per unit length for different bus size. The feature size is 0.18µm, T=H=0.18µm amd S=1.32µm,0.66µm and 0.33µm for 8,16 and 32 bit bus respectively.

	C1/e	C2/e	C1(for Sio2 as dielecrtic)
8-bit Bus	0.1363	0.1387	0.0470 pf/µm
16-bit Bus	0.2727	0.2083	0.0941 pf/µm
32-bit Bus	0.5454	0.4821	0.1883 pf/µm

We can see from the table that the both formula reduces the capacitance by approximately the same factor by which the bus size is decreases.That's the result because we are able to increase the spacing bteween the adjcent conductors if bus size reduces with assuming same area for bus.

Here are some links on related works:

A. Wire Sizing and Spacing:

1. Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance

2. A New Approach to Simulteneous Buffer Insertion and Wire Sizing

3. Optimal Non-Uniform Wire-Sizing under the Elmore Delay Model

4. Simulteneous Buffer & Wire Sizing for Performance and Power Optimization.

5. Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization.

6. EWA-Exact Wire Sizing Algorithm.

7. Modelling and Layout Optimization of VLSI Devices and Interconnects in Deep Submicron design.

8. An Efficient Approach to Simulteneous Transistor and Interconnect Sizing.

9. Closed Form Solution to Simulteneous Buffer Insertion/Sizing and Wire Sizing.

10. Optimal Shape Function for a Bi-Directional Wire under Elmore-Delay Model.