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Abhishek Mitra's Binary Encoded Papyrus =)Back |
Publications |
Journal |
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| A.Mitra, M.Skrzypczak, K.Ginalski, M.Rowicka, "Strategies for achieving high sequencing accuracy for low- diversity samples and avoiding sample bleeding on Illumina platform", Article, PLOS ONE, 2015.
a) Link to ISMB 2012 Poster.
b) Script for using HiSEQ TIFFS with OLB.
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| X.Li, Y.Zhao, B.Tian, M.Jamaluddin, A.Mitra, J.Yang, M.Rowicka, A.R.Brasier, A.Kudlicki, "Modulation of Gene Expression Regulated by the Transcription Factor NF-kappaB/RelA", Article, Journal of Biological Chemistry, February 2014. Cited by 3
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| Yang J*, Mitra A*, Dojer N, Fu S, Rowicka M**, Brasier A**, "A probabilistic approach to learning chromatin architecture and accurate inference of the NF-kappaB/RelA regulatory network using ChIP-Seq", Nucleic Acids Research / Oxford Journals, June 2013. Cited by 12
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| N.Crosetto*, A.Mitra*, M.Silva, M.Bienko, N.Dojer, Q.Wang, E.Karaca, R.Chiarle, M.Skrzypczak, K.Ginalski, P.Pasero, M.Rowicka**, I.Dikic**, “Nucleotide-resolution DNA double-strand breaks mapping by next generation sequencing”, Nature Methods, Apr 2013. Cited by 20
(* Joint-First Authors, ** Co-Corresponding Authors) |
| Z. Guo, A. B. Buyukkurt, J. Cortes, A. Mitra, W. Najjar. "A Compiler Intermediate Representation for Reconfigurable Fabrics in International Journal of Parallel Programming (IJPP)", Springer. Cited by 69 |
Conference |
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| A.Mitra, M.Vieira, P.Bakalov, W.Najjar, V.Tsotras, "Boosting XML filtering through a scalable FPGA-based architecture", in Fifth Biennial Conference on Innovative Data Systems Research January 2009, Pacific Grove, CA, USA. Cited by 39. |
| A. Mitra, W, Najjar, L. Bhuyan, "Compiling PCRE to FPGA for Accelerating SNORT IDS", in the ACM/IEEE Symposium on Architecture for Networking and Communication Systems (ANCS), Orlando, FL, Dec. 2007. Cited by 129. |
| A.Mitra, Ge Yao,W.Najjar, "Performance Analysis of SGI RASC RC100 Blade on 1-D DWT", Poster, Reconfigurable Systems Summer Institute 2007 at UIUC, Urbana-Champaign, IL, USA. Cited by 3. |
| A.Mitra, Z.Guo, A.Banerjee,W.Najjar, "Dynamic Co-Processor Architecture for Software Acceleration on CSoCs" , International Conference on Computer Design 2006, Santa Clara, CA, USA. Cited by 10. |
| Z.Guo, A.Mitra,W.Najjar, "Automation of IP Core Interface Generation for Reconfigurable Computing", IEEE International Conference on Field Programmable Logic and Applications 2006, Madrid, Spain. Cited by 12. |
| A.Banerjee, A.Mitra, M Faloutsos, "Dude - Where’s my Peer", IEEE Globecom 2006. Cited by 5. |
| A.Mitra, A.Banerjee,W.Najjar, D. Zeinalipour-Yazti, V. Kalogeraki, D. Gunopulos, "High Performance, Low Power Sensor Platforms Featuring Gigabyte Scale Storage", SenMetrics MobiQuitous 2005. Cited by 36. |
| A.Banerjee, A.Mitra,W.Najjar, D. Zeinalipour-Yazti, V. Kalogeraki, D. Gunopulos, "Co-S: Ahigh performance Co-processing Sensor architecture for offloading sensing and data processing", IEEE SECON 2005. Cited by 33. |
| A.Banerjee, A.Mitra,W.Najjar, "Splitting the Sensor Node", Poster, ACM SenSyS 2005. Cited by 1. |
| A.Mitra, K Lahiri, M Lajolo,"SOFTENIT: A Methodology for Boosting the Software Content of System-on-Chip Designs", Poster, ACM GLSVLSI 2005. Cited by 2. |
| D. Zeinalipour-Yazti, V. Kalogeraki, D. Gunopulos, A. Mitra and W. Najjar, "Towards In-Situ Data Storage in Sensor Databases", Panhellenic Conference on Informatics, Greece, 2005. Cited by 14. |
| S. Neema, A. Mitra, A. Banerjee ,W. Najjar, D. Zeinalipour-Yazti, V. Kalogeraki, D.Gunopulos, "NODES: A Novel System Design for Embedded Sensor Systems", Poster,
IPSN SPOTS 2005. |
| A.Mitra, "Bit Error Analysis of New Generation Wireless Transceivers", IEEE International Conference on Communication Systems 2002, Singapore. Cited by 1. |
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