Amin Kalantar

I'm a Ph.D. student in the Department of Computer Science and Engineering at the University of California, Riverside. I received the B.Sc degree in computer engineering from Sharif University of Technology in 2017. My research interests include FPGAs and reconfigurable computing, High Level Synthesis, and computer architecture.

I'm currently looking for a summer internship to work on challenging problems.

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News

Dec 2020. Won 3rd place in Xilinx Adaptive computing Developer Contest!
Mar 2020. Accepted paper in Journal of Chemical Theory and Computation!
Nov 2018. Paper presentation at ICCAD'18, San Diego, CA.
June 2018. Accepted paper in ICCAD'18!

Projects

Notable Works

  • Hardware Security Module

    Designed for performance constrained applications, Hardware Security Module supports both symmetric and asymmetric algorithms, Digital signature and Hash functions. I was responsible for developing PKCS#11 protocol and also the main software program to control the FPGA board with register programming. In addition, I implemented the UART and PCIE interfaces for FPGA (Xilinx Virtix-6) communications.


  • Elevator Management System (EMS)

    As a four-membered team, we developed a management system to monitor and control the elevators of a complex. I was responsible for implementing CAN bus protocol for communications between the Raspberry Pi board and elevators main board.





    A short demo of monitoring and controlling elevators in Palladium mall (one of the most luxurious shopping centers in Tehran)

  • AES Encryption/Decryption Algorithm

    Implementation of AES Encryption/Decryption algorithm with Verilog HDL was the objective of this course project.


  • Face Detection Program

    Developed in C programming language, the program reads bitmap picture and then tries to find faces in the picture without using any image analysis libraries like OpenCV.


  • Dialogue among Civilizations Game

    A strategy based game developed in C++ and using QT for the graphics.


  • Sharif Compiler

    Design and implementation of a compiler for a made-up language called L were the objectives of this project. The L language is similar to C Programming language. The compiler consists of Scanner, Parser and Code generator.


  • Simple CPU

    Design and implementation of Control Unit and Data Path of a simple CPU were the tasks of this project. The CU of this processor was designed by both Microprogramming and Hardwired methods.


Resume

Main Research Interests

  • FPGAs and reconfigurable computing
    High Level Synthesis
    Computer-Aided Design
    Computer Architecture

Research Experience

Research Assistant at University of California, Riverside, under supervision of Dr. Philip Brisk

As my first project, I started working on a machine learning framework to predict FPGA performance and power without relying on analytical models or HLS tools in-the-loop.

Currently, I'm working on implementaion and optimization of sparse matrix-matrix multiplication on Convey's Wolverine FPGAs.

Research Assistant at Data Storage, Networks, and Processing Laboratory, under supervision of Dr. H. Asadi

In 2015 I joined the Reconfigurable Computing Group in DSN Lab. As my first project, I was working on a Heterogeneous Architecture for SRAM-Based FPGAs, which involved mapping circuits into alternative logic elements rather than traditional LUTs to consume less silicon area.

After that, I started working on algorithms to enhance the number of reconfigurations over NVM-based FPGA device lifetime . Using NVM-based FPGAs reduces the chip area, removes the boot-up time and, alleviates design complexity at the chip/board level since an additional on-chip or off-chip non-volatile storage is not required to store configuration bits.

Publications:

K. O'Neal, M. Liu, H. Tang, A. Kalantar, K. DeRenard, and P. Brisk, "HLSPredict: Cross Platform Performance Prediction for FPGA High-Level Synthesis", International Conference on Computer-Aided Design (ICCAD), San Diego, CA, USA. November, 2018

Skills

  • Programming Languages
    C/C++, Python, Assembly (MIPS and Intel8086), Matlab
  • Design, Synthesis and Simulation Tools:
    Xilinx ISE, Xilinx Vivado Design Suite, Synopsis Design Compiler, Synopsys Power Compiler, Hspice, Modelsim
  • FPGA Academic Tools
    VPR 7.0, ABC Berkley, ODIN
  • HDL
    Verilog
  • Operating Systems
    Windows, Linux
  • Typesetting
    Microsoft Office, Gnuplot, LATEX

Experiences

Teaching Assistant:

Sharif University of Technology

  • Logic Design, Dr. A. Hemmatyar
    Fall 2016
  • Operating Systems, Dr. H. Asadi
    Fall 2015
  • Digital Systems Design, Dr. S. Bayat-Sarmadi
    Fall 2015
  • Computer Structure and Language, Dr. H. Asadi
    Spring 2015, Fall 2014
  • Logic Design, Dr. A. Hemmatyar
    Spring 2015
  • Logic Design, Dr. S. Bayat-Sarmadi
    Spring 2014


Contact

  • Address:

    Department of Computer Science and Engineering
    University of California, Riverside
    900 University Ave, Riverside, CA

  • Email:

    akala006 [at] ucr.edu
    amin.kalantar94 [at] gmail.com

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