Philip Brisk: Research Agenda

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Research Agenda

Dr. Brisk’s research focuses on three key areas: Programmable Microfluidics and Laboratory-on-a-Chip technology, Application- and Domain-specific Processors, and FPGAs and Reconfigurable Computing. As the computing landscape evolves, new challenges continue to emerge, especially in terms of cost, parallelism, and programmability. Dr. Brisk’s research agenda aims to tackle the most timely and important problems within these three domains. 

Programmable Microfluidics

Laboratories-on-a-Chip (LoCs) based on microfluidic actuation technologies have the potential to automate and miniaturize repetitive laboratory experiments that are today performed by humans in domains such as enzymatic, proteomic, and DNA analysis, drug discovery, clinical diagnostics, and many others. Advances in LoC technology offer the potential to significant improve public health worldwide and lead to significant advances in clinical diagnostics and medicine. The application executed on a LoC is called an assay: a microfluidic algorithm built from primitive operations. LoC technology is poised replace manual execution of assays via automation, miniaturization, and programmability.

Dr. Brisk’s research on LoCs focuses on two key topics:
  ♦  How are LoCs designed?
  ♦  How are LoCs programmed?

The design topic emphasizes the creation of software tools to assist with LoC design, coupled with optimization algorithms to automate key steps of the design process; the programmability topic emphasizes the creation of domain-specific languages and compilers targeting software-programmable LoCs.

Application- and Domain-specific Processors
With Dennard Scaling having broken down in 2006 and the end of Moore’s Law on the horizon, fewer and fewer opportunities remain to improve processor performance and reduce power consumption. Application- and domain-specific specialization through custom hardware acceleration realized via hardware/software co-design is in many respects the last frontier. From mobile Systems-on-a-Chip (SoCs) to industrial data centers, hardware specialization is on pace to play an ever-increasing role in society’s computing infrastructure.

The objective of this research is to capture and characterize emerging applications that can benefit from hardware acceleration just before they become mainstream. The application analysis determines the computational and energy bottlenecks of each application. The initial research step is to tune the application to achieve the highest possibly performance and/or energy consumption on a representative platform. From there, bottlenecks are removed through hardware specialization. This process iterates until all bottlenecks are removed or the cost of removing each remaining bottleneck does not justify the benefits of further specialization.

Application domains of particular interest (at the moment) include:
  ♦  Time-series data analysis algorithms for the Internet of Things (IoT)
  ♦  Machine learning, computational statistics, and computer vision
  ♦  DNA sequencing and bioinformatics workloads

Field Programmable Gate Arrays (FPGAs)
Companies such as Microsoft and Amazon are rapidly integrating FPGAs into their data centers, while Intel has recently purchased Altera, a leading FPGA vendor. For applications amenable to acceleration, FPGAs offer significant performance and energy consumption benefits compared to processors, and can also accelerate many applications that do not compile easily onto GPUs, while offering energy improvements to many applications that compile onto both. However, FPGAs are not a panacea: they are notoriously difficult to program (and it is unlikely that data center programmers will want to learn hardware design methodologies based on languages such as VHDL and Verilog), compile times may take tens of minutes or even hours, and they do not provide the traditional notion of an address space or a memory hierarchy.

Dr. Brisk’s research on FPGAs addresses these challenges:
  ♦  Domain-specific language and compiler design for FPGAs
  ♦  Reduction of FPGA compile times
  ♦  Memory models, including coherence, consistence, and virtualization, for FPGA-based accelerators
  ♦  Cutting-edge FPGA applications

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