Lab 1: Introduction to Cadence & Schematic Capture

  In the labs for this course, you will see the Cadence set of tools for VLSI design. These tools are the state -of-the-art CAD tools widely used in the industry. This software is very large and it is difficult to learn it entirely in one quarter. We will try to learn a part of it, which is very useful in digital IC design. The various tools learned during the labs would be used at the end for the project. So make sure you understand each lab properly.

  In this lab you will be introduced to some basics of Cadence tools as well as schematic capture and simulation of schematic. Then we¡¯ll build the first circuit, as shown in figure (1) below, using the Cadence Composer tool.

1.Invoke CIW(Command Interpreter Window)

1. Log onto hercules.cs.ucr.edu by putty (make sure log on using ssh)

2. source /usr/local/cadence/usecadence

3. export DISPLAY=yourmachineIP:0

4. download cds.lib, save to your home directory(ie. /cadence/yourlogonname)

10. To start Cadence, execute icfb& By now you should have a CIW window pop up. This is called Command Interpreter Window or CIW as shown like this

In addition to this window,you should also have a library manager window popped out. icfb uses Library Manager for browsing through all the libraries.

Some Useful Notes: Saving and Restoring Cadence Session Variables

Saving the System Environment to a file

Referring to Section (2), step #3, to save the working environment. The software will also

save any other environment variables found in other tools/windows (schematic and

simulation windows).

Select Options => Save Defaults, then click OK to save the file to your root directory.

Notice the warning message in the CIW indicating that the file .cdsenv did not exist

before, and the system will create a new one. You may also save multiple system

environment files to different file names and different directories, then edit and load these

files in different environment sessions.

Saving the System State to a file

The system "State" saves all the windows and simulation results of your current session.This helps in case you want to continue later from where you stopped, but do not want to go through the full steps again. It¡¯s mainly useful if you need to logout, or even when taking a long break! Cadence may "hang" if you leave it unattended for a prolonged period of time, especially if you are running on a slow machine, and locked your screen. This is an added security feature of the environment.

To save a simulation session to be able to reload it later from a "clean" CIW run:

1. Go to the CIW and select Options => Save Session.

2. Click OK on the window displaying the default name cdsSession.save. The file is saved in your working directory.

Restoring the System Environment

To load a saved default environment file, with the Cadence software running, type the following in the CIW¡¯s Input Line:

envLoadFile("~/.cdsenv")

Restoring the System State

1. In a new Unix session, you can now start Cadence by typing the alias word cadence at a terminal prompt. The CIW appears after some time.

2. At the CIW¡¯s command prompt, type: load("cdsSession.save")

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Notes: Cadence Tools Environment

Verilog-XL is the Digital Circuits Simulation tool in the Cadence environment.

Analog Artist is the Analog Circuits Simulation tool in the Cadence environment.

Virtuso is the Layout Editing tool in the Cadence environment.

The Cadence environment uses 3 major initialization files:

cds.lib: sets the path to the libraries used which contain the various components/cells.

.cdsinit: customizes specific simulation environments, i.e. the Analog Artist¡¯s.

.cdsenv: sets the global Cadence environment.

 As an example, if you¡¯ll be simulating an analog design, the following 3 steps may be required to ensure that our symbol is generated using the "analog template".  we¡¯re listing these steps to familiarize you with the Cadence directory and file structure. In addition, you¡¯ll need to edit this file later to adopt it to your individual analog simulation environment preferences.

1. Go to the directory: /CMC/tools/cadence/IC/tools/dfII/samples/artist/

2. Copy the file cdsinit to your working directory (cadence), and rename it to .cdsinit

3. You may read through the file to familiarize yourself with it¡¯s contents, however, at this stage, you do not need to modify it.

A symbol cellview (representation) of a design could be automatically generated in Cadence to represent a design category (analog, digital, etc...) that you had created. Each design category has a different Symbol Configuration Template (STC), which dictate how the symbol is automatically generated. The various symbol template configurations are stored under the following directory:

/CMC/tools/cadence/IC/tools/dfII/samples/symbolGen/

The Cadence default template for generating a symbol view is the digital template, which is stored under the file name default.tsg. A symbol is a black box representing a circuit.

An analog design uses the artist.tsg configuration file (used by Analog Artist).

A digital design uses the default.tsg configuration file (used by Verilog-XL).

For Analog Artist, make sure the artist symbol generation template is used in your design, by assuring the following command is present in your .cdsinit file:

schSetEnv("tsgTemplateType" "artist")

Certain environment variables may not be accessible otherwise. Always keep backup copies in case you decide to revert to the original.

2.Create libraries

1.In your home directory (~/), make a directory in which you want subsequent Cadence files to be stored in. Let's   call this directory cadence. To do this, execute the command at the unix prompt: mkdir ~/cadence.

Then you can also create a sub-directory to the cadence directory, called Mylib. In Mylibs, you will store all your design libraries and cells in order to organize your work. Type mkdir ~/cadence/Mylibs

2. On the CIW banner, select File => New => Library.

3. Under Library, Name, type mylib_rlc

4. Under Library, Path (non-library directories), choose ~/cadence/Mylibs .

5. Under Technology File, select No tech library needed.

This step adds a new entry to your cds.lib file"defining" the new library name and path.Click on OK

6. Now, if you look at your Library Manager Window, you should see mylib_rlc as one of the libraries in the left most column. If you didn't have the library manager window at the first place, you can open it by going to the CIW window and clicking on Tools-->Library Manager.

3. Creating a new design

1. Now, from the CIW, select File => New => Cellview, and fill in the form as shown below in order to define the new rlc schematic cellview. Library name mylib_rlc. In the Cell Name field, type rlc. In the Tool selection, choose Composer-Schematic. This automatically defines the View Name to schematic. Here, we note in Tool the various design entry tools. Click OK.

               

An empty Composer Window now appears, as shown next.Before proceeding, note that the CIW performed some background operations, among which, it "attached a default techfile (cdsDefTechLib) to the library mylib_rlc", as read from the CIW output area.

               

4. Schematic Capture

The process of editing a design is called schematic capture. You can use several methods in the Cadence environment tools to achieve the same effect. We could select from the pull-down menus, or click on one of the icons on the left of the design entry form, or use a shortcut letter, referred to as a Bindkey. Browse through the icons on the left in the Composer Window, and note the "floating description" on each.

You will build the first circuit as shown below:

               

4.1 Placing the Instances

1. Click on the Instance Icon. The add instance form appears.

2. Select the following: Under the Library column, select analogLib. Under Cell, select res. Under View, select symbol. The Browser¡¯s window displays as shown below. There¡¯s no need to close it when done, as we¡¯ll need it later.

               

3. Move the cursor to the Composer schematic window, and note the res symbol following it. Also, note that the Add Component window has expanded to display various other parameters. Before you click on the schematic window to place the resistor symbol, edit the Add Instance form by modifying the Resistance value to 22K Ohms, as shown below.

               

4. Now click in the composer window to place the resistor.

5. Another resistor symbol follows the cursor. Place it in the window then click on Cancel on the Add Instance window. The form disappears.

6. Add the other instances symbols from the analoglib as indicated below:
C (analoglib, cap) = 47n F
L (analoglib, ind) = 500m H
Ground (analoglib, gnd)

7. To rotate the input resistor, click once on it to select (left-click with the mouse),  to open the auxiliary menu. Select Rotate. Alternatively, click on it and press the "r" bindkey.

4.2 Adding the I/O Pins

1. To add the input and output pins, click on the Pin icon in the lower left side of the Composer window. The Add Pin form appears.

2. Under Pin Names, type Vin Vout. Note that Direction in the form reads input, as shown below.

               

3. Click once on the schematic window. The first pin is placed. Note the other pin¡¯s symbol follows the cursor as you move across the window. The Add Pin form is still active, but with only Vout displaying in the Pin Name field.

4. On the Add Pin form, change Direction to read Output. Place the Vout pin in the schematic window.

4.3 Connecting Wires

1. To connect the wires, click on the icon Wire(narrow). Activate the Composer-Schematic Window by clicking on its Title Bar.

               

2. While the Add Wire window is still displaying (but not selected), click on the s key on your keyboard. This snaps the wires to connect between the little diamond-shapes displaying by the nodes.

4.4 Modifying Instance Properties

To modify the properties of each instance, click once to select each individual instance, then click on the q key (query) on your keyboard. This is the same as selecting the instance, then centre-clicking using the mouse, then selecting the Properties form.

               

Modify the Resistance, Inductance (500m H), and Capacitance (47n F) property of each instance. Refer to the overall schematic. By default, Cadence automatically writes the Instance Name.

4.5 Checking and Saving

To check and save the schematic, click on the design icon on the left, Check and Save. Notice the Cadence¡¯s CIW displays the following messages:
Extracting "rlc schematic"
Schematic check completed with no errors.
"mylib_rlc rlc schematic" saved.

If you get Warnings/Errors:

Congratulations!  You have just completed your first schematic in Cadence.

QUICK USAGE REFERENCE:

1. Press 'p' to add pins
2. Press 'q' on the device/instance to edit properties for the device
3. Press 'w' to add wires
4. Press 'f' to fit the schematic in your schematic window.
5. Press 'l' to label a wire.
6. Press 'Up' and 'Down' arrows to move up and down within a schematic window.
7. Press 'ESC' to terminate any of the operations in the schematic window.

5. Creating the Symbol Cellview

Now we¡¯ll create a symbol (black box) to represent our circuit. The symbol Cellview will be created based on the already-available schematic Cellview. This is called creating a Cellview from another Cellview.

1. Copy the file .cdsinit to your home directory . This sets the symbol generation to "Artist".

2. From the Composer schematic window, select Design => Create Cellview => From Cellview...   This sequence creates symbols automatically, based on their primary input and output pins. The Cellview From Cellview form appears as shown below. Change "Tool/Data Type" to Symbol, then click OK.

               

3. On the new form that appears, select the "Load/Save" button. The form expands.

4. In the form¡¯s lower left section, change the cyclic field next to ""Load" to "Artist".

5. Click on the "Load" button to load the Analog Symbol Generation Template.

6. If a message appears calling to "Overwrite Base Cell CDF", click on No so as not to overwrite the inherited parameters in the base cell Component Descripton Format.

7. A new Composer-Symbol Editing window appears.

8. In the Symbol Editing Window, the outside red box defines the selection region when selecting the symbol if it¡¯s present on a schematic design. The inside green box defines the dimension of the symbol as it would show when placed in a schematic design.Expand both, and drag and drop the square pins, the cdsName, and the connecting terminals as shown in figure next.

The cdsTerm("Vout") is a label that displays the pin names or the net names (Vout)

The cdsParam(1,2,3) are labels that display parameters of an instance, e.g. 75 Ohm

The cdsName("") is a label that displays the instance or cell name, e.g. rlc1

9. Click on the icon named Label.

10.In the Label field, type RLC. Change the Font Height to 0.15. Press Enter to place the label. Click on Cancel on the form to close it.

The symbol should look as in figure below.

11.Now press the Save icon in your design window. The CIW should display the message: "rlc symbol" saved.

12.From the pull-down menus of thee Composer Symbol Editor, select Window => Close.

13.The Composer-Schematic Editing window should be still open. Close it using Window => Close.

The produced symbol will be used in the TestFixture. This is a circuit model that¡¯s used to test the performance of a design. It will incorporate input signal sources, power, ground, the circuit load (which could have a variable parameter, e.g. the capacitance, CAP, varying from 1n F down to 1p F in 3 steps: 1n F, 500p F, 1p F), and the positive and negative supply rails (buses).

6 Creating the TestFixture (testbench)

We¡¯ll now create a new schematic cell using the rlc symbol as one of its instances.

1. From the Cadence CIW, go to:

File => New => Cellview...

Fill it as shown below., creating a new Cell called test_rlc, with a schematic cellview.

               

2. Click OK. A new Composer-Schematic window appears.

3. Connect your new circuit using components according to the following table, and referring to the schematic figure next (figure 13).

4. To add the wire names, click on the Wire Name icon.

5. Under Names, type in Vin Vout. Click OK. The name Vin follows the mouse as you move over the schematic window. Click on the input wire as shown in next figure to place it. The name Vout next follows the mouse pointer. Repeat for Vout.

6. Click on the Check and Save icon when done.

TABLE 1. RLC test Fixture Circuit Components

Library Name Cell Name View Name Properties/Comments *
mylib1 rlc Symbol no parameters
analogLib vsin Symbol

AC Magnitude=1, Amplitude=50m, Frequency=1M, Offset Voltage=0

analogLib cap Symbol Capacitance=1p
analogLib gnd Symbol no parameters

* Scale Factors (case-sensitive):

M= Mega (10^6) k= kilo (10^3) m= milli (10^-3) u= micro (10^-6)

n= nano (10^-9) p= pico (10^-12) f= femto (10^-15) a= atto (10^-18)

Note (1): No space between the number and the scale factor (i.e. 1p, for 1 pico Farad)

Note (2): Do not include the units, as they are predefined in the instance properties file.

FIGURE 13. The RLC testFixture schematic

6.0 Attaching the Border

Borders are added to the design the same way as we add instances, i.e. from a library.

Your working directory now contains a text file called cds.lib which you copied earlier.This file lists all the paths to the libraries that you can use. By default, if you had not copied it, Cadence would have automatically created a standard one and placed it in your working directory. The new design library mylib_rlc that you created should be listed now in the cds.lib file.

The cds.lib file should list a line that shows the path to the US_8ths borders library.

1. Click on the Instance icon, and select the US_8ths library, and a suitable border, i.e. select the Asize Cell Name. A border follows the mouse. On the Composer window, you may click on the Zoom-out-by-2 icon to easily display the border boundaries.

2. Move the border to the center of the window, and click once to place it. You may then press the Esc key, or click Cancel on the form.

3. You may now wish to select the entire circuit, and drag it to a more central position.

4. To edit the title of the sheet, from the pull down menus in Composer, select Sheet => Edit Title. A form appears. Fill it in as shown below, then click OK, and note the changes on the schematic design¡¯s title block.

               

FIGURE 14. Title Block Properties window

5. On the schematic window, press the bindkey f (fit) to display the full schematic.

6. To select the whole design, go to the farthest top left corner of the schematic, left-click

once, then, without releasing the mouse, drag to the other corner of the circuit. You can

then click once and drag the design to another more central location, then click last to

place it. Make sure you then click outside the circuit area to unselect.

7. To add text to make the schematic more illustrative, go to Add => Note => Note Text...

8. Type in the Note Text Box: Top Level 4-Bit Ripple Adder

9. Change the Height to (0.15)

10.A Text Box follows the mouse. Place it under the schematic, then press the Esc key.

7.0 Check & Save, and Exiting Composer

1. Click on the Check and Save icon in the Composer window.

2. You may now close all the open schematic windows.

We¡¯ll next discuss simulating the design.

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