UCR CS168: Introduction to VLSI Design, Winter 2003

Week 1

Lab1(01/07): Introduction to Cadence & Schematic Capture

Lab Report: Due by the end of next lab(01/09) (Cancelled)

Lab2(01/09): Analog Simulation of Passive Circuits

Lab Report: Due by the end of next lab(01/14)

      Announcement: Since Dr. Vahid's researchers need to run simulation on soc, cadence is disabled on soc. Right now only hercules.cs.ucr.edu is accessible to CS168 students. Because some of you may lose your work of lab1, you are not required to submit the lab1 report this time. But we still need to do the simulation on your design of lab1, you have to repeat what you did on lab1 on hercules this time.  

      Several things you need to pay attention when you repeat your work this time:

Week 2

Lab3 (01/14) Inverter circuit design and simulation

Lab4 (01/16) Cancelled

Week 3

Cadence Using Notice: Cadence can not work well if all students try to do work at once. The way we can keep the load down is to kill extraneous processes. You can kill your own cadence process that was not normally terminated.

1) Stop using cadence

2) Run this command: ps -ef | grep $logname | grep cadence | awk '{print $2}' | xargs kill -9

In addition to that, system group would help us to kill all jobs at 2AM every day in case cadence totally crash. So be cautious to save your work before 2AM everyday.

Lab5 (01/21) Continue lab3 work

    You can skip Layout versus Schematic Check step.

Lab S173 Card Access Notice: The general access to this lab is revoked from now on. Only TA and some legitimate users could use card to get in. So the lab work would be required to be finished only at lab time. Considering the restrictive usage of the cadence, some of the lab work may allow longer time to do.

Lab6 (01/23) Continue lab3 work.

After you create your complete inverter layout, follow the following steps when you do simulation:

Inverter Simulation Steps

Report due by the end of next Tuesday (01/28):           

1. Submit the plot of

• inverter circuit schematic view
• inverter circuit symbol view
• inverter circuit test schematic view
• inverter layout view (Make sure it passed design rule check, you will continue using it in following labs)
• inverter extracted extracted view (Make sure it corresponds to your circuit view)

Simulation result submission:

• inverter circuit simulation waveform result (mark out the rising delay and fall delay) and write in your report.
• inverter extracted layout Tran analysis simulation waveform result (also mark out the rising delay and fall delay) and write in your report.
• inverter extracted layout parametric analysis simulation waveform: Please explain your simulation result.

Week 4

Lab 7 (01/28) Create your own cell library

Lab 8 (01/30) Continue on lab7

Week 5

Lab 9 (02/04) Hierarchical Design - 4-bit Adder Simulation

Notice: For the adder to work, we still need to attach it to NCSU_TechLib_hp06 technology library. 

Do the following: In the Library Manager => select your adder library => press right button 

                    => Attach Design Library to Tech files => attach your library to NCSU_TechLib_hp06

Week 6

Lab 10 (02/11) Create a 4-16 bit Decoder

Design Notice: You can use additional logic control block.

Extension Notice: this lab is due on next Thursday (02/20)

Week 7

4-16 bit Decoder

Week 8

Project: SRAM cache design