| Instructor: | Jun Yang |
| Office: | SURGE 318 |
| Telephone: | 909-787-2558 |
| Email: | junyang@cs.ucr.edu |
| Course Web Page |
| Class Meeting Time: | 2:10-3:30pm, TR |
| Lecture Room: | OLMH 1212 |
| Office Hours: | 3:30-5:00, TR |
| Textbook: | John L. Hennessy and David A. Patterson, |
| "Computer Organization and Design, The Hardware/Software Interface," | |
| 2nd Edition. Morgan Kaufmann Publishers, 1998. | |
| Reference Books: | Hans-Peter Messmer |
| "The Indispensable PC Hardware Book," | |
| 4th Edition. Addison-Wesley, 2001. | |
| Prerequisite: | (CS061 (C- or better) AND CS120A) OR EE120A |
| Blackboard System: | http://www.ilearn.ucr.edu/ |
| TA's | Jia Yu: Office hours Friday 11-1 Surge 281 |
| Satya Mohanty: Office hours Wednesday 2-3pm Surge 281 | |
| Lab meeting time: | W, 11:10-2pm Surge 171 (TA: Jia Yu); Fri, 8:10-11pm Surge 170 (TA: Satya Mohanty); Fri, 8:10-11am Surge 171 (TA: Jia Yu) |
| Lab attendance is mandatory. You are expected to stay in the lab for the entire lab session, working on material related to this course. Part of your lab grade is based on attendance and participation |
Labs must be finished on-time. Each student should demo the lab to the TA to get credit. Late labs will not be accepted. Individual labs may also require additional information such as waveforms or a summary of results.
Note: For Lab 6,8,10, you need to turn in to WWWTurnIn Directory before deadline. There is penalty for late turnin.
| Description | Due Time | |
|---|---|---|
| Week 1 | Lab1: Tutorial of VHDL and Aldec HDL environment | |
| Week 2 | Lab2: Design of 8-bit ALU | Lab 1 |
| Week 3 | Lab3: Design of 8-bit Multiplier | Lab 2 |
| Week 4 | Lab4: FSMD Design of Fibonacci Calculator | Lab 3 |
| Week 5 | lab5 Design of MIPS Datapath | Lab 4 due |
| Week 6 | Lab5 Design of MIPS Datapath | |
| Week 7 | Lab7: Design of MIPS controller | Lab5 due |
| Week 8 | Lab7: Design of MIPS controller | |
| Week 9 | Lab9: Cache Simulator | Lab7 |
| Week 10 | Lab9: Cache Simulator | Lab 9 |