CS122A: Lab 2

Introduction

The Digilab Digital I/O daughterboard features a 4-digit, 7-segment LED unit. Normally, four separate 7-segment LEDs would demand 32 pins from the FPGA: 7 segments (cathodes) * 4 digits + 4 shared anodes (1 for each digit). To reduce the number of pins used, the corresponding segments of each digit share a connection:

What does this configuration entail? If you wanted to display the number "1234", you would need to configure the 7 cathodes to display a "4" and enable the first digit (the one's place). Then you would need to configure the cathodes to display a "3" and enable the second digit, and so on (the order is not crucial). When each digit is displayed at a short enough interval, a human perceives the appropriate number as being displayed solidly, without any flickering. Rapidly switching between tasks in this manner is known as time multiplexing. For the first part of this lab, you will write a VHDL entity that does this.

Start a new project in ISE6 named lab2 (Verify that you are saving to your home directory - /home/csmajs/yourlogin, most likely should be mapped to Drive H. If not, ask a TA.).
Create a "led_7seg_driver" entity.

Your driver entity should have the following interface (you can rename the I/Os as needed):

The input consists of 4 concatenated 4-bit binary numbers that correspond to what you want to display on the LEDs. For example, if you want to display "1234" you would set input to "0001,0010,0011,0100" (without the commas).

Hint: You may want to use two processes in your LED driver:

A process that enables one of the four digits every clock cycle and stores the number corresponding to that digit in a signal accessible by both processes, and...
A process that enables the appropriate bits of the sseg output depending on the number stored in the shared signal.

Hint: You may find the DIO4 Reference Manual useful.

When reset is enabled, you should display nothing on the LEDs.

Add the clock divider from Lab 1 to your design.
Modify the clock divider so that it outputs a clock signal with a period of 4ms

Hint: The Digilab board has a 50MHz oscillator with a period of 1/50,000,000 = 20ns. We need a period of 4ms or 4,000,000 ns.

Write a top-level entity that connects the clock divider to your LED driver.
Add a 16-bit signal to your top entity and connect it to the LED driver's input. The signal should be set to a constant that causes the LED driver to display "5678".
Create a UCF file for your design by referring to the Interconnect Table provided by Digilent.

Hint: The boards are connected such that the "C" headers are in use. On each page of the Interconnect Table, there are only two columns you should be concerned with.

Check out a Digilab board. You must show your UCF file to a TA before you can check out a board.
Download your design to a Digilab board and demonstrate it to a TA.

Part 2

Create a binary to binary-coded decimal (BCD) converter entity named bindec_converter.

The purpose of the converter is to take an input and convert it into a form that your led_7seg_driver can display. In other words, you will need to extract the numbers for the thousand's place, hundred's place, ten's place, and one's place.

This can be achieved by using a set of counter variables or signals for each place. You can then subtract from the original number to determine the value for each place.

For example, given an input vector of 122, we can take the following steps:

Initialize counter variables or signals to 0. Note that the input is 00000001111010 (122).
Is 122 greater than or equal to 1000? No.
Is 122 greater than or equal to 100? Yes. Subtract 100 and increment hundred's place counter.
Is 22 greater than or equal to 100? No.
Is 22 greater than or equal to 10? Yes. Subtract 10 and increment ten's place counter.
Is 12 greater than or equal to 10? Yes. Subtract 10 and increment ten's place counter.
Is 2 greater than or equal to 10? No.
Output the newly-converted number: 0000,0001,0010,0010 (without the commas).

The above algorithm can be represented as an FSMD in the following manner (modified 10/6):

Take the partially-complete FSMD above and model a complete version of it in VHDL.

Hint: Here is an example of an enumerated type definition: type colors is (RED, GREEN, BLUE);

Hint: You should use at least two separate processes in your VHDL code, one acting as a state register and another consisting of combinational logic.

When reset is enabled, your converter should output 0s.

If the input is larger than can be displayed on the LEDs, you should output the last four digits of the number. You may need to add additional states to implement this.

Connect your converter to your LED driver in your top-level entity
Connect the 8 switches on the Digital I/O board to the lower 8 bits of your converter's input line and connect the 5 buttons on the Digital I/O board to the next 5 bits of input. Use a '0' for the 14th bit.
Demonstrate your design to a TA.
Isolate your VHDL and UCF files into a folder in your home directory and turn them in to the designated turnin folder (one per group).

Do not leave any files on the local machine you are working on! Verify that your files are saved to your home directory.

The entities you have written for this lab should be very useful in the future (hint, hint); don't delete your code!