CS122A: Lab 1

Steps

Complete the Active-HDL Tutorial.
In Active-HDL, write a 2x4 decoder using the following skeleton code:

-- decoder_2x4.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder_2x4 is
	-- declare input and output ports of the decoder
end decoder_2x4;

architecture bhv of decoder_2x4 is
begin
	-- add behavioral description of the decoder
end bhv;

(Hint: A 2x4 decoder has a single 2-bit input and enables a single bit of a 4-bit output based on the input)

Test the behavior of your decoder using the waveform editor (no testbench is needed).
In Active-HDL, write a 2-bit counter using the following skeleton code:

-- counter_2bit.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter_2bit is
	-- declare input and output ports of the counter 
end counter_2bit;

architecture bhv of counter_2bit is
begin
	-- add behavioral description of the counter
end bhv;

Note: Your counter must have a reset and clock input.

Test the behavior of your counter using the waveform editor (no testbench is needed).
In Aldec-HDL, create a top-level component that will connect the decoder and counter using the following template:

-- lab1_top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top is
	-- declare input and output ports of the top-level entity
end top;

architecture bhv of top is
	-- declare the counter and decoder input
	-- declare any intermediate signals
begin
	-- declare any port mappings
end bhv;

Write a testbench for your design. Your testbench must enable the reset signal and disable it, followed by at least four cycles of the clock signal.
Have your testbench and Active-HDL design checked off by a TA.
Complete the Xilinx ISE 6 Tutorial.
Create a new design in ISE6 called lab1.
Import your top, decoder, and counter entities (you can just copy and past them into new source files) into ISE6.
Add the following clock divider component to your design:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clockdiv is
	port(
		clock:	in STD_LOGIC;
		output:	out STD_LOGIC
	);
end clockdiv;

architecture bhv of clockdiv is
	signal output_temp: STD_LOGIC := '0';
begin
	process (clock)
		variable count: integer range 0 to 50000000;
	begin
		if (clock = '1' and clock'event) then
			if (count = 12499999) then
				output_temp <= not output_temp;
				count := 0;
			else
				count := count + 1;
			end if;
		end if;
		output <= output_temp;
	end process;
end bhv;

Why is the clock divider necessary? The Digilab's clock runs at 50MHz. At that rate, you would not be able to perceive any change in the LED output.

In your top entity, insert the clock divider between the real clock and the clock input of your counter.
Add the following constrants to your design (rename as needed):

NET "clock"			LOC = "P182";
NET "reset"			LOC = "P187";

NET "output<0>"			LOC = "P111";
NET "output<1>"			LOC = "P109";
NET "output<2>"			LOC = "P102";
NET "output<3>"			LOC = "P100";

NET "ledgp"			LOC = "P45";

The four output pins are connected to four of the eight LEDs on the Digial I/O daughter board. You must also enable the ledgp signal to "activate" the LEDs:

Add an output port to your top-level entity called ledgp.
In your top-level entity's architecture, add ledgp <= '1';. It does not matter if this is before the port maps or after (remember that statements outside of a process run concurrently).

You are now ready to download your design to a board.

Check out a Digilab board (one per group).
Synthesize, implement, and download your design to the Digilab board.
Have your work for this step checked off by a TA.
Isolate your VHDL and UCF files to a new folder in your home directory and turn them in to the designated turnin folder.