Homework 1 CS 122A: Intermediate Embedded and Real-Time Systems Prof. Frank Vahid, Dept. of CS&E, UC Riverside Assigned: Tuesday Oct 4 Due: Tuesday Oct 11, submit at beginning of lecture (9:40 am), or before then at Prof. Vahid's office ENGR2 328 (slide under door if closed) Study groups strongly encouraged. Groups of three or more working together for at least one hour get 10% extra credit. Don't submit identical homeworks, though -- each person should work through every problem on his/her own and writeup his/her solution. Study groups serve the purpose of helping each other understand the problems, helping each other when stuck, and comparing answers. However, answers should be different -- especially for problem 1. Estimated time: About 2.5 hours total: 1.5 hours for the tradeoff problems, and 1 hour for the remaining problems. Please record your actual times and include them along with your submission (see last problem). 1. (1 point) (Tradeoffs) You are contracted by a customer to design a portable MP3 player. The customer, who doesn't understand the distinction between design metrics and design parameters, and who confuses issues, gives you the following list of "requirements." Convert the customer's list into two lists, a metric and a parameter list, and rewrite the customer's descriptions to more precisely represent each metric or parameter. The MP3 player's requirements include: * Should have 8 control buttons, one for each of the player's 8 operations. But because size should be small enough to fit in a pocket, we could double up the operations onto just 4 buttons. * Batteries should be easy to find in stores and cheap. Size constraints allow use to go with one 9-volt battery or one or two AA batteries. One 9-volt has about 10,000 Joules and costs about $1, while one AA battery also has about 10,000 Joules but costs only about 50 cents. So two AAs may be best, since we also want longest battery lifetime. 2. (2 points) (Tradeoffs) Given the metrics, parameters, and other information shown below for the design of a portable fingerprint recognition system: (a) Compute how many possible implementations exist (b) Create a table that in a left column lists four solutions (one solution per row) representing good tradeoffs, and in a right column quantitatively and qualitatively describes the tradeoffs among the metrics for each implementation Metrics: Performance (faster is better, no hard constraint), size (smaller is better, hard constraint is <=100,000 gates), cost (cheaper is better) Parameters: Type of processor (68HC12 or ARM7) Number of each processor Information: Each 68HC12 is 30,000 gates Each ARM7 is 45,000 gates The fingerprint recognition algorithm requires 1 million computations. A 68HC12 requires 0.1 milliseconds per computation An ARM7 requires 0.06 milliseconds per computation If more than one processor is used, the computations are perfectly divisible among those processors. Each 68HC12 costs $0.50 (50 cents). Each ARM7 costs $1.25 (1 dollar and 25 cents). 3. (1 point) A designer wishes to a create VHDL combinational process but creates the following (A, B, C, D, and F are all signals): process (A, B, C) begin F <= (A and B) or (not(A) and B and C) or (A and not(B) and D); end process; (a) What's wrong with this process description, i.e., why doesn't it represent combinational logic? (b) Using waveforms, clearly show why this process has memory, and thus isn't combinational logic. 4. (1 point) (a) Write a combinational VHDL process for an adder that adds two integers A and B, and has one integer output S. Be sure to have the correct process sensitivity list. (b) Repeat (a), except build a "vector adder." In this case, assume A, B, and S are each arrays of 32 integers. The adder should compute S(1) = A(1) + B(1), S(2) = A(2) + B(2), etc. (Hint: use the for loop construct rather than writing out 32 equations). 5. (1 point) Write sequential VHDL for a finite-state machine that sets an output bit P to 1 whenever the FSM detects two 1s during successive clock cycles on an input A. Any additional successive 1s should NOT result in P=1, until a 0 again appears on A. So the input sequence 0110111111000001010100000111000 ^ ^ ^ would result in P=1 only for the cycles pointed to by the ^ above. Use two processes, one for the state register, and one for logic. 6. (2 points) Trace the event queues for signals S and T and for port D (ports are signals), and the relationship of the event queues to the generated waveforms, for the VHDL code below simulated for 5 ns. D is an output port of type integer. signal S: integer; process() variable v : integer := 1; begin D <= 0; S <= 1; T <= 0; if (v = 1) then T <= 9; end if; wait for 1 ns; S <= S + 1; D <= S + v; T <= T + 1; wait for 1 ns; v := 3; S <= v after 1 ns; T <= v ; D <= v + S + T; wait for 2 ns; // Note the wait for 2 ns, not 1 ns S <= T; T <= S; wait; end process; 7. (No points) * (a) Actual time spent on tradeoff problems: ______________ (b) Actual time spent on remaining problems: ______________