CS 122A: Intermediate Embedded and Real-Time Systems
Prof. Frank Vahid, Dept. of CS&E, UC Riverside
Thu, 9/30/04
Due: Thu, Oct 7.
Study groups strongly encouraged. Groups of three or more working
together for at least one hour get 5% extra credit. Don't submit
identical homeworks, though -- each person should work through every
problem on his/her own and writeup his/her solution. Study groups
serve the purpose of helping each other understand the problems,
helping each when stuck, and comparing answers. However, answers
should be different -- especially for problem 1.

Estimated time: 2 hours for problem 1, 1 hour total for all remaining 
problems.  Please report the time spent per problem on your homework. 
Reported time will not contribute to the grade, but helps us adjust 
homework problem difficulty.

1. (7 points) You are asked to implement a smoothing filter that outputs the
   averages of the past four samples appearing at a 12-bit input P. 
   Your filter should take a clock input P_sample that pulses whenever
   P should be sampled. Your boss tells you that you can use one
   of the following devices: an 8051 microcontroller, an ARM 
   microprocessor, or a Xilinx Spartan FPGA. (Note: each device comes in 
   multiple versions).
   
   (a) Provide a tradeoff analysis for your boss. Include the following
      * A definition of FOUR design metrics (goals) that are likely
        to be relevant to a filter design.
      * A description of THREE design parameters and their possible values. 
        The choice of which class of device is one of those parameters, 
        having three possible values (8051, ARM or Spartan).
      * A description (not a design) of SIX different designs 
        implementations, obtained by selecting design parameter values.
        The designs should span a broad range of designs.
      * A table comparing the five implementations with respect to the
        four design metrics.
  
   (b) Assume that high performance (fast sampling rate) is top priority.
       Explain which design implementation would be best.

   (c) Assume low unit cost is top priority. Explain which design 
       implementation would be best.

   This problem will require you to do some research on the web to determine
   product features.

   All analysis should be QUANTITATIVE whenever possible. Thus, don't 
   say "Part A has low cost." Rather, say "Part A costs $5" and provide
   a reference. Likewise, don't say "Implementation X takes longer to design."
   Rather, say "Implementation X would take about 2 weeks to design" and
   explain briefly why.
 
   The report will be graded based on:
      * Selection of relevant design metrics
      * Selection of relevant design parameters
      * Selection of design implementations representing a broad range
      * Quantitative analysis
      * Conciseness
      * Lucidity 
   Your answer to part (a) will likely be 2-3 pages long, while parts
   (b) and (c) just a short paragraph each.

2. (2 points)
   (a) Write a combinational VHDL process for a comparator that compares
       two integers A and B, and has outputs A_lt_B (A < B), A_eq_B (A = B),
       and A_gt_B (A > B). Be sure to have the correct sensitivity list.
   (b) Repeat A, except assuming A and B are arrays of 10 integers each,
       and the comparator compares the sums of the two arrays. (Hint:
       use the for loop construct).

3. (2 points) Write sequential VHDL for a finite-state machine that
   sets an output bit P to 1 whenever the FSM detects three or more
   0s on an input bit A. As long as 0s continue to appear, the FSM
   holds P at 1, returning P to 0 when the next input 1 appears.
   Note: use two processes (state register, and logic).

4. (2 points) Show the event queues for signal s and port D (ports are 
   signals), and the relationship of those queues to the generated timing 
   diagram, for the VHDL code below, simulated for 3 ns.

   D is a port of type integer.

   signal S: integer;
   process()
      variable v : integer := 0;
   begin
      v := v + 1;      
      S <= S + v;
      D <= S;
      wait for 1 ns;
   end process;

5. (1 point) 
   (a) In the context of wanting to create a process representing 
       combinational logic, how does a synthesis tool interpret a signal 
       that is read by a process but does not appear in the process' 
       sensitivity list?
   (b) In the context of wanting to a create a process representing
       sequential logic, how does a synthesis tool interepret a process
       representing a state register but having clk, reset, AND the
       next state signal in the process' sensitivity list?