Simulation Tutorial: VHDL Design of a 1-bit adder and a 4-bit adder

Symphony EDA Simulation Tutorial:
VHDL Design Of A 1-bit Adder And 4-bit Adder

I. Introduction

In this lab the functionality of a design, in our case a 1-bit adder, is written in a Hardware Description Language (HDL). The correctness of the design is verified at the software level through simulation, thus saving critical design time. The 1-bit design is then expanded to a 4-bit adder by structurally connecting four 1-bit adders.

II. Procedure

Creating the 1-bit adder

Create a directory for all the VHDL code you write in this class in your home directory by using the command "mkdir cs120b".

Start Symphony by running /usr/bin/start-sonata.

Choose File/New Workspace, and choose the name "lab1a". For Workspace location, choose the VHDL folder you just created.

Choose File/New to create a new file.

The following is the VHDL code for the 1-bit adder. Enter the code as seen below into the empty file. NOTE: All lines that start with "--" are not needed. These are comments to help you better understand what the actual code is doing.

-- Simulation Tutorial
-- 1-bit Adder

-- This is just to make a reference to some common things needed.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- We declare the 1-bit adder with the inputs and outputs
-- shown inside the port().
-- This will add two bits together(x,y), with a carry in(cin) and 
-- output the sum(sum) and a carry out(cout).
entity BIT_ADDER is
        port( a, b, cin         : in  STD_LOGIC;
              sum, cout         : out STD_LOGIC );
end BIT_ADDER;

-- This describes the functionality of the 1-BIT adder.
architecture BHV of BIT_ADDER is
begin
        
        -- Calculate the sum of the 1-BIT adder.
        sum <=  (not a and not b and cin) or
                        (not a and b and not cin) or
                        (a and not b and not cin) or
                        (a and b and cin);

        -- Calculates the carry out of the 1-BIT adder.
        cout <= (not a and b and cin) or
                        (a and not b and cin) or
                        (a and b and not cin) or
                        (a and b and cin);
end BHV;

Now choose File/SaveAs. Navigate to ~/cs120b/lab1a.sym, choose "lab1a.vhd" for the filename, and click Save.

Choose Compile/Compile file... A window might pop up asking if you want to add the file to your project. Select YES. Now your code will begin compiling. If you have any errors you'll see them in red in the bottom window.

Creating testbench for the adder.

The testbench is provided for you and is located here (right click and do a 'save target as'). Save the file in your vhdl/lab1a directory
On the upper left window of Symphony you should see your Workspace. Right click on "Library lab1a => ....." and choose "add files to Lab1a", selecting the "add_tst.vhd" file you just downloaded.
Click on the "+" to the left of your "Library lab1a" workspace to expand the file list. You'll see two files, lab1a.vhdl which you copied, and add_tst.vhd which you downloaded. Double click on add_tst.vhd to take a look at the file.
Choose "Compile/CompileAll" to compile the files in our project.

Simulating the design.

Select Simulate/Select Top Level and choose "test_add(test)". This is the testbench that we're going to simulate to ensure the correctness of our design.

Select Simulate/Go and the simulation window will pop up. In the bottom left window of your screen you'll see a list of signals. Drag and drop each of these signals into the "Signals" table in the top middle of the screen.

Select Simulate/Run All, and you'll see some waveforms generated by the adder. The waveform represents the circuit inputs and outputs at any given point in time -- the testbench supplied the inputs, and the circuit generated the outputs.

Click on the waveform at some point and verify that the adder is working correctly. You don't really even need to do this - the testbench contains assert statements that check the output against the known correct output. If there's a mismatch, you would have seen an error message.

Creating and testing the 4-bit adder

Create a New Workspace by selecting the File and choosing New Design. The design should be called adder4.

Download the add4.vhd file and the add4_tst.vhd file, and add them to your project.

Compile both files, select the top level test entity, and simulate the design.

View the simulation to verity that the 4-bit adder functionality is correct.

Note that there are only four test-cases in the provided code. You have to add FOUR more unique test cases, each of which you need to include the correct 'assert' statement. Show the results of your test-bench to your TA.

What to turn in:

Demo the design to your TA. You will also need to do the www turn-in for both your report (wait until you finish 1b to do the lab report) and your testbench.