EE/CS120B introduces the exciting and rapidly-growing field of embedded computing systems.
In EE/CS120B, you'll learn how to develop and program embedded systems. It will introduce you to using a unified view of hardware and software design, mapping desired functionality to a collection of single-purpose processors (digital hardware and peripherals) and general-purpose processors (microprocessors). Students will gain experience building real digital systems using VHDL, synthesis and FPGAs (Xilinx), and programming embedded microprocessors (Intel 8051 8-bit microcontroller).
| Instructor | Kris Miller, ( kmiller@cs.ucr.edu), Office: SURGE Bldg. 341, Office hours: MW 2:00pm - 3:00pm |
|---|---|
| Lecture | TR 9:40am-11am LSPW 2418 |
| Lab | Section 021: MW 6:10pm-10pm SURGE Bldg. 173 |
| Textbooks | Embedded System Design: A Unified Hardware/Software Approach,
Vahid and Givargis, Wiley & Sons, 2002, Accompanying Web page
Logic and Computer Design Fundamentals, M. Morris Mano, Charles R. Kime, Prentice Hall, , 2nd Ed. Accompanying Web page RECOMMENDED: VHDL Design Representation and Synthesis, Gray Armstrong, Prentice Hall, Second edition, ISBN 0130216704, OR another VHDL book covering synthesis. All students should have a basic C programming book. A good C book is The C Programming Language, Kernighan and Ritchie, Prentice Hall, ISBN 0-13-110362-8. An 8051 microcontroller book may be helpful for the lab. A good one is The 8051 Microcontroller, by Stewart and Miao, Prentice Hall, Second edition, ISBN 0-13-531948-x. |
| Software | We'll be using the Keil 8051 C compiler, Philips 8051 emulators/software,
the Aldec VHDL simulator, and Xilinx/Synopsys Foundation Express.
You may want to consider purchasing Aldec VHDL simulator student edition. It's an easy to use yet powerful VHDL simulator written for windows. You might also consider getting the Xilinx Student Edition Software and FPGA Board |
| TAs | Shawn Nematbakhsh( snematbakhsh@cs.ucr.edu), Petko Bakalov( pbakalov@cs.ucr.edu) Office hours: in lab |
| Prerequisite | CS/EE120A (Logic Design) |
| Mailing list | 120B Mailing List: It is your responsibility to subscribe to the mailing list with a UCR email address. Some announcements, and your scores during the quarter, will be sent to that email address. If you commonly read email from another address (e.g., yahoo or hotmail), then you must still provide us with your UCR address, but you might then create a .forward file in your UCR account for your more common address. |
| Grade | Lab component 40% (lab assignments, lab attendance, in-lab exams),
Lecture component 60% (homeworks 10%, quizzes 10%, Midterm 20%, Final 20%)
Note: To ensure minimum competency in both the principles and practice, you must pass both components to pass the course; likewise, you must achieve at least a C- in both components to achieve a C- or better in the course. |
| Workload | This is a 5-unit course. You should plan to spend 3 hours/week in lecture, 8 hours/week in lab, and 6-8 hours doing individual study (readings, homeworks, programming, lab preparation, etc.). Don't underestimate the individual study time -- be sure to allocate that time into your weekly schedule. 6-8 hours represent the real time required by successful students. |
No late homeworks. Submitted homeworks should be neat and legible -- sloppy or unnecessarily long homework submissions may lose points or may not be graded. You probably want to do a draft of the homework, and then create a neater copy to turn in.
Lab policy
Cheating will be punished severely. For those who don't want others' cheating to cheapen your own hard work and hurt your grade -- there is an anonymous cheating reporting form at: https://www.cs.ucr.edu/cheating/. While students may discuss material generally (and this is encouraged!), ASSIGNMENT SUBMISSIONS MUST REPRESENT INDEPENDENT WORK .