UNIVERSITY OF CALIFORNIA, RIVERSIDE
Department of Computer Science and Engineering
Department of Electrical Engineering
EE/CS120A - Logic Design
Summer 1 2001

Schedule: Lecture: 6/25/01 - 7/28/01, MTWR, 8:00 - 9:30AM, Sproul Hall 2340.
Laboratory:

  • Lab 1: MTWR, 3:00 - 6:00PM, Bourns Hall B265
  • Lab 2: MTWR, 3:00 - 6:00PM, Bourns Hall B144

    Textbook:

  • Digital Design Principles & Practices, J. Wakerly, Prentice Hall, 2001, 3rd Ed.
  • A VHDL Primer, J. Bhasker, Prentice Hall, 2000, 3rd Ed.

    Instructor: Dr. Enoch Hwang. Office: BRNHL A303. e-mail: ehwang@cs.ucr.edu. Office hours: Immediately after class. More detail and updated information on the web at www.cs.ucr.edu/~ehwang.

    Prerequisites: CS10.

    Objective: To learn the principles of digital logic design focusing on combinational logic circuits. Computer-aided design (CAD) and engineering of digital systems.

    Topics: (Numbers in parenthesis are Wakerly sections.)

    1. Introduction. Digital devices. Integrated Circuits (ICs). Digital-Design Levels. CAD Tools (1).

    2. Number systems, conversions, arithmetic in binary, negative numbers (2).

    3. Digital circuits, simple gates (3.1). Adder.

    4. Boolean Algebra and Logic Design.

      5. Basic theorems, boolean functions (4.1), minterms & maxterms, canonical and standard forms (4.1.6).
      Technology mapping

    5. Simplification of Boolean Functions.

      6. n-cubes (2.14), Karnaugh maps, simplifying expressions (4.3.4). "don't-care" (4.3.7).
      Quine-McCluskey (tabulation) method (4.4).

    6. Combinational Components.

      7. adder/subtractor (5.10),
      ALU (5.10), multiplexers (mux) (5.7),
      decoders (5.4),
      encoders (5.5),
      three-state devices (5.6),
      comparators (5.9),
      ROM (10.1, 10.1.1),
      PLA (5.3).

    7. VHDL (4.7)

    8. Miscellaneous

      9. Transistor Implementations (3.3),
      Hazard-Free Design (4.5).
      Transistors on a chip as seen through an electron microscope.

    9. Sequential Logic

      10. Latches, Flip-flops (7.2).

    Holidays: 7/4/01.

    Tests: Two midterms: Tue. Jul. 3 and Tue. July 17. Final: Friday July 27, 2001, 7:30AM - 9:30AM.

    Grading: Homeworks 10%, Labs 30%, 2 Midterms @ 15% each, Final 30%. You must get at least 50% or the class average on the test (whichever is smaller ) on two of the three tests to pass the course.

    Grades:

    Homeworks:

    Solutions:

    Labs:

    VHDL links:

  • Summary of VHDL commands
  • Complete VHDL reference guide.
  • VHDL Lab examples
  • Online VHDL tutorial
  • Online VHDL textbook: VHDL Cookbook
  • VHDL synthesis tutorial
  • Simple VHDL examples
  • Free Peak VHDL simulator and synthesizer
  • $45 Aldec VHDL simulator and synthesizer student edition
    •

    Other related links:

  • 74xx Datasheets
  • Complete IC Datasheets
  • Online VLSI Design Tutorial
  • History of the transistor
  • Free Acrobat reader
    •