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Super Simple Processor Design Project

The goal of this project was to produce a fully synthesizable processor with the simplest instruction set possible. Currently it performs 32-bit operations, but is limited to 18-bit loads. Maximum clock speed for this processor is currently 118 mhz.

Instruction Set

loadi	Load immediate from program memory
loadm	Load memory from RAM
store	Store memory into RAM
add	Sum of two regiesters
subt	Difference of two registers
and	Logical and of two registers
or_r	Logical or of two registers
Xor_r	Logical xor of two registers
shr_r	Shift right operand
shl_r	Shift left operand
sign	Check for sign, used for jump is less than zero
jnz	Check for zero, used for jump if not zero
halt	Halt the program

Through following the steps below you can download and simulate samples programs I have provided below, or even write your own simple "assembly like" code and assemble it into the machine language by use of the "assemble" program provided. UCR in no way endorses claims, guarantees, or promises of any kind implied or otherwise that may be found within.

Step 1:	Download and untar the provided source files from below.

Step 2:	Edited assembly source file you are interested on running on the processor(such as mult or gcd) and insert values you wish to process. Alternatively you can create your own assembly source files if you are careful to use only the instructions available in the proper format(see section on creating your own assembly source files below). Now run the assemble program on your file(usage: assemble ). This has created the "rom" file for the processor. Also you need to adjust the testbench file so that the assert is what your expected output is. Set the wait for this assert longer than the process should take.

Step 3:	Simlulate the processor with synopsys using the script file provided, zsim.scr. You may have to set permissions to run this file. If you wish to track the wave forms as the simulation runs, click the Misc button, then hierarchy browser. Select through the components and find the targets that you wish to track. After double clicking, the waveform window should appear. If it is empty, close it and reselect the target until it appears(bug?). Next click view, then full name to display only the filename(you can also compress here if you have more than fit in the window). Now click back to the debugger and in the box next to run input the time to run the simulation for. You may continue running, so if you're interested in watching the waveform as it progresses you can enter a relatively small amount, say 1000. Otherwise enter slightly more than the testbench assert wait time you entered earlier.

Step 4:	To synthesize the processor, run the script zsyn.scr. After each file has been analyzed(this could take some awhile), edit each gate file that was created. Comment out the line 15, that begins with "type UNSIGNED is array (INTEGER ", by adding -- to the beginning of the file. Next run the script file zgatesim.scr. Now you can simulate the synthesys in the same way you did before.

Source Files Tarred

vhdl files	All vhdl source files and scripts needed to run the simulations and synthesys.
assembler	The assembler program including C++ source file and a readme containing guidlines for writing programs to be assembled with this.

Individual Files With Descriptions

scpu_alu.vhd	Arithmatic logic unit, where all mathmatic operations are conducted
scpu_cntrl.vhd	Control unit, handles the states and signal changes for each state
scpu_lib.vhd	Library file that contains all constant variables
scpu_master.vhd	This unit's sole purpose is to tie all the other units together
scpu_mux.vhd	3X1 multiplexor unit
scpu_obuff.vhd	tri-state buffer that prevents output until program has halted
scpu_ram.vhd	The program's RAM storage
scpu_reg.vhd	32-bit register file
scpu_rom.vhd	Program memory(ROM)
scpu_shftr.vhd	Shifter unit to shift left or right
scpu_sign.vhd	Returns the sign of the word that is passed in
scpu_tb.vhd	Test bench file with assert statement to check for correct output
scpu_zero.vhd	Checks whether passed in word is equal to zero
assemble	Executable to assemble simple programs into ROM files
div	Simple program for division
fibonacci	Simple program to execute fibonacci sequence
gcd	Simple program to calculate greatest common divisor
main.cc	Source file for assemble program
makefile	Makefile for compiling assemble source
mult	Simple program to preform multiplication
onesCnt	Simple program to perform binary "ones count"
power	Simple program to raise int to int power
sign	Simple program to determine sign of a value

Limitations and Future Additions This processor currently cannot take in a 32-bit value. A combination load high and load low will need to be written into to achieve this. Also the processor currently does not check for overflow and needs to do so. Very large numbers can be generated that will start yielding wrong results in this version. Another side goal of this project that was not reached at this time is writing a translator so that code from a "C++ like" compiler, which generates low level assembly output, can be written and run on this processor. Look for updates in the future by myself, or another student.

Project designed by: Randy January

Comments can be sent to me at rjanuary@cs.ucr.edu