library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; package CONV_PACK_LC2_all is -- define attributes attribute ENUM_ENCODING : STRING; end CONV_PACK_LC2_all; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity register_file is port( clk, DR_enable : in std_logic; DR_address, SR1_address, SR2_address : in std_logic_vector (0 to 2); data_in : in std_logic_vector (0 to 15) ; SR1_out, SR2_out : out std_logic_vector (0 to 15)); end register_file; architecture SYN of register_file is component FD1 port( D, CP : in std_logic; Q, QN : out std_logic); end component; component FDS2L port( D, CP, CR, LD : in std_logic; Q, QN : out std_logic); end component; component ND4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component AN3 port( A, B, C : in std_logic; Z : out std_logic); end component; component NR3 port( A, B, C : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal member46_12_port, larray355_7_1_port, larray355_1_15_port, larray355_7_11_port, larray355_3_3_port, larray_1_5_port, larray_5_7_port , larray355_2_9_port, member185_13_port, larray_5_12_port, larray355_2_0_port, larray355_0_13_port, member46_2_port, larray_4_4_port , larray355_6_2_port, larray355_7_8_port, larray_2_10_port, larray_0_6_port, larray_4_14_port, larray_5_3_port, larray_3_12_port, larray_1_1_port, larray355_3_7_port, larray_4_9_port, larray355_7_15_port , larray355_1_11_port, larray355_7_5_port, larray_0_2_port, larray_2_14_port, larray_4_10_port, larray_4_0_port, member46_6_port, larray355_6_6_port, larray355_6_13_port, larray_1_8_port, larray355_2_4_port, larray_5_8_port, larray355_6_4_port, larray355_0_15_port, larray355_6_11_port, member46_4_port, member185_15_port, larray355_2_6_port, larray_0_0_port, larray_4_12_port, larray_4_2_port, member46_14_port, larray_0_9_port, larray355_3_5_port, larray355_1_13_port, larray_5_1_port, larray355_7_7_port, larray_3_10_port, larray_1_3_port, larray_5_14_port, larray_4_6_port, member46_0_port, member185_11_port, larray_2_12_port, larray355_3_8_port, larray_0_4_port, larray355_2_2_port, larray355_0_11_port, larray355_6_15_port, member46_10_port, member46_9_port, larray_1_7_port, larray355_6_0_port, larray355_6_9_port, larray_5_10_port, larray_5_5_port , larray_3_14_port, larray355_7_3_port, larray355_7_13_port, larray355_3_1_port, larray355_5_5_port, larray_6_9_port, larray355_4_12_port, member185_6_port, larray355_1_7_port, larray_6_11_port, larray_0_15_port, larray_3_1_port, larray_7_3_port, larray_3_8_port, larray355_0_4_port, larray355_3_10_port, larray355_5_14_port, larray355_4_6_port, larray_1_13_port, larray_6_0_port, larray_2_2_port, larray_7_7_port, larray_6_15_port, larray355_0_9_port, larray_0_11_port, larray_3_5_port, larray355_1_3_port , larray355_2_12_port, larray355_5_1_port, larray_2_6_port, member185_2_port, larray355_5_8_port, larray_7_13_port, larray_6_4_port, larray355_4_2_port, larray355_5_10_port, larray355_3_14_port, larray355_0_0_port, larray355_4_0_port, member185_0_port, larray355_5_12_port, larray355_0_2_port, larray_2_4_port, larray355_1_8_port, larray_1_15_port, larray_6_6_port, larray_7_11_port, larray355_1_1_port, larray355_2_10_port, larray355_4_14_port, larray355_5_3_port, member185_9_port, larray_7_5_port, larray355_4_9_port , larray_0_13_port, larray_3_7_port, larray_1_11_port, larray_7_15_port, larray_6_2_port, larray_2_0_port, member185_4_port, larray355_0_6_port, larray_7_8_port, larray355_3_12_port, larray_6_13_port, larray355_4_4_port, larray_3_3_port, larray_7_1_port, larray355_5_7_port, larray_2_9_port, larray355_2_14_port, larray355_4_10_port, larray355_1_5_port, larray_6_3_port, larray_7_14_port, larray_1_10_port, larray_2_1_port, member185_5_port, larray355_3_13_port, larray355_0_7_port, larray355_4_5_port, larray_7_9_port, larray_6_12_port , larray_3_2_port, larray_7_0_port, larray355_4_11_port, larray355_2_15_port, larray355_5_6_port, larray355_1_4_port, member185_1_port, larray_2_8_port, larray355_4_1_port, larray355_0_3_port , larray355_5_13_port, larray355_1_9_port, larray_2_5_port, larray_7_10_port, larray_1_14_port, larray_6_7_port, larray355_1_0_port, larray355_5_2_port, member185_8_port, larray355_2_11_port, larray355_4_15_port, larray355_4_8_port, larray_7_4_port, larray_0_12_port, larray_3_6_port, larray_0_10_port, larray_7_6_port, larray_6_14_port, larray_3_4_port, larray355_0_8_port, larray355_1_2_port , larray355_5_0_port, larray355_2_13_port, larray_2_7_port, larray_6_5_port, larray_7_12_port, larray355_5_9_port, larray355_4_3_port , larray355_0_1_port, larray355_3_15_port, member185_3_port, larray355_5_11_port, larray_6_8_port, larray355_4_13_port, larray355_5_4_port, larray355_1_6_port, member185_7_port, larray_0_14_port, larray_6_10_port, larray_3_0_port, larray_7_2_port, larray_3_9_port, larray355_3_11_port, larray355_5_15_port, larray355_0_5_port, larray355_4_7_port, larray_1_12_port, larray_6_1_port , larray_2_3_port, member185_10_port, larray_4_7_port, larray_0_5_port, larray_2_13_port, larray355_3_9_port, larray355_2_3_port, member46_11_port, member46_8_port, member46_1_port, larray355_6_1_port, larray355_0_10_port, larray355_6_14_port, larray_1_6_port, larray_5_4_port, larray_3_15_port, larray_5_11_port, larray355_6_8_port, larray355_7_2_port, member46_5_port, larray355_3_0_port, larray355_7_12_port, larray_5_9_port, larray355_0_14_port, larray355_6_10_port, larray355_6_5_port, larray355_2_7_port, member185_14_port, larray_4_13_port, larray_0_1_port, larray_4_3_port, member46_15_port, larray_0_8_port, larray355_1_12_port, larray355_3_4_port, larray355_7_6_port, larray_5_0_port, larray_5_15_port , larray_3_11_port, larray_1_2_port, larray_5_2_port, larray_3_13_port, larray_1_0_port, larray355_1_10_port, larray355_7_14_port, larray_4_11_port, larray_0_3_port, larray_4_8_port, larray355_3_6_port, larray355_7_4_port, larray_2_15_port, larray_4_1_port, larray355_6_12_port, member46_7_port, member46_13_port, larray355_6_7_port, larray355_2_5_port, larray_1_9_port, larray355_7_0_port, larray355_3_2_port, larray355_7_10_port, larray355_1_14_port, larray355_2_8_port, larray_1_4_port, larray_5_6_port , larray_5_13_port, member185_12_port, larray355_2_1_port, member46_3_port, larray355_6_3_port, larray355_0_12_port, larray_4_5_port , larray355_7_9_port, larray_4_15_port, larray_0_7_port, larray_2_11_port , n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766, n767, n768, n769, n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n783, n784, n785, n786, n787, n788, n789, n790, n791, n792, n793, n794, n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810, n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843, n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, n918, n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940, n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951, n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008 , n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023 : std_logic; begin SR1_out_reg_15_label : FD1 port map( D => member46_15_port, CP => clk, Q => SR1_out(0), QN => open); SR1_out_reg_14_label : FD1 port map( D => member46_14_port, CP => clk, Q => SR1_out(1), QN => open); SR1_out_reg_13_label : FD1 port map( D => member46_13_port, CP => clk, Q => SR1_out(2), QN => open); SR1_out_reg_12_label : FD1 port map( D => member46_12_port, CP => clk, Q => SR1_out(3), QN => open); SR1_out_reg_11_label : FD1 port map( D => member46_11_port, CP => clk, Q => SR1_out(4), QN => open); SR1_out_reg_10_label : FD1 port map( D => member46_10_port, CP => clk, Q => SR1_out(5), QN => open); SR1_out_reg_9_label : FD1 port map( D => member46_9_port, CP => clk, Q => SR1_out(6), QN => open); SR1_out_reg_8_label : FD1 port map( D => member46_8_port, CP => clk, Q => SR1_out(7), QN => open); SR1_out_reg_7_label : FD1 port map( D => member46_7_port, CP => clk, Q => SR1_out(8), QN => open); SR1_out_reg_6_label : FD1 port map( D => member46_6_port, CP => clk, Q => SR1_out(9), QN => open); SR1_out_reg_5_label : FD1 port map( D => member46_5_port, CP => clk, Q => SR1_out(10), QN => open); SR1_out_reg_4_label : FD1 port map( D => member46_4_port, CP => clk, Q => SR1_out(11), QN => open); SR1_out_reg_3_label : FD1 port map( D => member46_3_port, CP => clk, Q => SR1_out(12), QN => open); SR1_out_reg_2_label : FD1 port map( D => member46_2_port, CP => clk, Q => SR1_out(13), QN => open); SR1_out_reg_1_label : FD1 port map( D => member46_1_port, CP => clk, Q => SR1_out(14), QN => open); SR1_out_reg_0_label : FD1 port map( D => member46_0_port, CP => clk, Q => SR1_out(15), QN => open); SR2_out_reg_15_label : FD1 port map( D => member185_15_port, CP => clk, Q => SR2_out(0), QN => open); SR2_out_reg_14_label : FD1 port map( D => member185_14_port, CP => clk, Q => SR2_out(1), QN => open); SR2_out_reg_13_label : FD1 port map( D => member185_13_port, CP => clk, Q => SR2_out(2), QN => open); SR2_out_reg_12_label : FD1 port map( D => member185_12_port, CP => clk, Q => SR2_out(3), QN => open); SR2_out_reg_11_label : FD1 port map( D => member185_11_port, CP => clk, Q => SR2_out(4), QN => open); SR2_out_reg_10_label : FD1 port map( D => member185_10_port, CP => clk, Q => SR2_out(5), QN => open); SR2_out_reg_9_label : FD1 port map( D => member185_9_port, CP => clk, Q => SR2_out(6), QN => open); SR2_out_reg_8_label : FD1 port map( D => member185_8_port, CP => clk, Q => SR2_out(7), QN => open); SR2_out_reg_7_label : FD1 port map( D => member185_7_port, CP => clk, Q => SR2_out(8), QN => open); SR2_out_reg_6_label : FD1 port map( D => member185_6_port, CP => clk, Q => SR2_out(9), QN => open); SR2_out_reg_5_label : FD1 port map( D => member185_5_port, CP => clk, Q => SR2_out(10), QN => open); SR2_out_reg_4_label : FD1 port map( D => member185_4_port, CP => clk, Q => SR2_out(11), QN => open); SR2_out_reg_3_label : FD1 port map( D => member185_3_port, CP => clk, Q => SR2_out(12), QN => open); SR2_out_reg_2_label : FD1 port map( D => member185_2_port, CP => clk, Q => SR2_out(13), QN => open); SR2_out_reg_1_label : FD1 port map( D => member185_1_port, CP => clk, Q => SR2_out(14), QN => open); SR2_out_reg_0_label : FD1 port map( D => member185_0_port, CP => clk, Q => SR2_out(15), QN => open); reg_reg_7_0_label : FDS2L port map( D => larray355_7_0_port, CP => clk, CR => n896, LD => DR_enable, Q => larray_7_0_port, QN => open); reg_reg_7_1_label : FDS2L port map( D => larray355_7_1_port, CP => clk, CR => n897, LD => DR_enable, Q => larray_7_1_port, QN => open); reg_reg_7_2_label : FDS2L port map( D => larray355_7_2_port, CP => clk, CR => n898, LD => DR_enable, Q => larray_7_2_port, QN => open); reg_reg_7_3_label : FDS2L port map( D => larray355_7_3_port, CP => clk, CR => n899, LD => DR_enable, Q => larray_7_3_port, QN => open); reg_reg_7_4_label : FDS2L port map( D => larray355_7_4_port, CP => clk, CR => n900, LD => DR_enable, Q => larray_7_4_port, QN => open); reg_reg_7_5_label : FDS2L port map( D => larray355_7_5_port, CP => clk, CR => n901, LD => DR_enable, Q => larray_7_5_port, QN => open); reg_reg_7_6_label : FDS2L port map( D => larray355_7_6_port, CP => clk, CR => n902, LD => DR_enable, Q => larray_7_6_port, QN => open); reg_reg_7_7_label : FDS2L port map( D => larray355_7_7_port, CP => clk, CR => n903, LD => DR_enable, Q => larray_7_7_port, QN => open); reg_reg_7_8_label : FDS2L port map( D => larray355_7_8_port, CP => clk, CR => n904, LD => DR_enable, Q => larray_7_8_port, QN => open); reg_reg_7_9_label : FDS2L port map( D => larray355_7_9_port, CP => clk, CR => n905, LD => DR_enable, Q => larray_7_9_port, QN => open); reg_reg_7_10_label : FDS2L port map( D => larray355_7_10_port, CP => clk, CR => n906, LD => DR_enable, Q => larray_7_10_port, QN => open); reg_reg_7_11_label : FDS2L port map( D => larray355_7_11_port, CP => clk, CR => n907, LD => DR_enable, Q => larray_7_11_port, QN => open); reg_reg_7_12_label : FDS2L port map( D => larray355_7_12_port, CP => clk, CR => n908, LD => DR_enable, Q => larray_7_12_port, QN => open); reg_reg_7_13_label : FDS2L port map( D => larray355_7_13_port, CP => clk, CR => n909, LD => DR_enable, Q => larray_7_13_port, QN => open); reg_reg_7_14_label : FDS2L port map( D => larray355_7_14_port, CP => clk, CR => n910, LD => DR_enable, Q => larray_7_14_port, QN => open); reg_reg_7_15_label : FDS2L port map( D => larray355_7_15_port, CP => clk, CR => n911, LD => DR_enable, Q => larray_7_15_port, QN => open); reg_reg_6_0_label : FDS2L port map( D => larray355_6_0_port, CP => clk, CR => n912, LD => DR_enable, Q => larray_6_0_port, QN => open); reg_reg_6_1_label : FDS2L port map( D => larray355_6_1_port, CP => clk, CR => n913, LD => DR_enable, Q => larray_6_1_port, QN => open); reg_reg_6_2_label : FDS2L port map( D => larray355_6_2_port, CP => clk, CR => n914, LD => DR_enable, Q => larray_6_2_port, QN => open); reg_reg_6_3_label : FDS2L port map( D => larray355_6_3_port, CP => clk, CR => n915, LD => DR_enable, Q => larray_6_3_port, QN => open); reg_reg_6_4_label : FDS2L port map( D => larray355_6_4_port, CP => clk, CR => n916, LD => DR_enable, Q => larray_6_4_port, QN => open); reg_reg_6_5_label : FDS2L port map( D => larray355_6_5_port, CP => clk, CR => n917, LD => DR_enable, Q => larray_6_5_port, QN => open); reg_reg_6_6_label : FDS2L port map( D => larray355_6_6_port, CP => clk, CR => n918, LD => DR_enable, Q => larray_6_6_port, QN => open); reg_reg_6_7_label : FDS2L port map( D => larray355_6_7_port, CP => clk, CR => n919, LD => DR_enable, Q => larray_6_7_port, QN => open); reg_reg_6_8_label : FDS2L port map( D => larray355_6_8_port, CP => clk, CR => n920, LD => DR_enable, Q => larray_6_8_port, QN => open); reg_reg_6_9_label : FDS2L port map( D => larray355_6_9_port, CP => clk, CR => n921, LD => DR_enable, Q => larray_6_9_port, QN => open); reg_reg_6_10_label : FDS2L port map( D => larray355_6_10_port, CP => clk, CR => n922, LD => DR_enable, Q => larray_6_10_port, QN => open); reg_reg_6_11_label : FDS2L port map( D => larray355_6_11_port, CP => clk, CR => n923, LD => DR_enable, Q => larray_6_11_port, QN => open); reg_reg_6_12_label : FDS2L port map( D => larray355_6_12_port, CP => clk, CR => n924, LD => DR_enable, Q => larray_6_12_port, QN => open); reg_reg_6_13_label : FDS2L port map( D => larray355_6_13_port, CP => clk, CR => n925, LD => DR_enable, Q => larray_6_13_port, QN => open); reg_reg_6_14_label : FDS2L port map( D => larray355_6_14_port, CP => clk, CR => n926, LD => DR_enable, Q => larray_6_14_port, QN => open); reg_reg_6_15_label : FDS2L port map( D => larray355_6_15_port, CP => clk, CR => n927, LD => DR_enable, Q => larray_6_15_port, QN => open); reg_reg_5_0_label : FDS2L port map( D => larray355_5_0_port, CP => clk, CR => n928, LD => DR_enable, Q => larray_5_0_port, QN => open); reg_reg_5_1_label : FDS2L port map( D => larray355_5_1_port, CP => clk, CR => n929, LD => DR_enable, Q => larray_5_1_port, QN => open); reg_reg_5_2_label : FDS2L port map( D => larray355_5_2_port, CP => clk, CR => n930, LD => DR_enable, Q => larray_5_2_port, QN => open); reg_reg_5_3_label : FDS2L port map( D => larray355_5_3_port, CP => clk, CR => n931, LD => DR_enable, Q => larray_5_3_port, QN => open); reg_reg_5_4_label : FDS2L port map( D => larray355_5_4_port, CP => clk, CR => n932, LD => DR_enable, Q => larray_5_4_port, QN => open); reg_reg_5_5_label : FDS2L port map( D => larray355_5_5_port, CP => clk, CR => n933, LD => DR_enable, Q => larray_5_5_port, QN => open); reg_reg_5_6_label : FDS2L port map( D => larray355_5_6_port, CP => clk, CR => n934, LD => DR_enable, Q => larray_5_6_port, QN => open); reg_reg_5_7_label : FDS2L port map( D => larray355_5_7_port, CP => clk, CR => n935, LD => DR_enable, Q => larray_5_7_port, QN => open); reg_reg_5_8_label : FDS2L port map( D => larray355_5_8_port, CP => clk, CR => n936, LD => DR_enable, Q => larray_5_8_port, QN => open); reg_reg_5_9_label : FDS2L port map( D => larray355_5_9_port, CP => clk, CR => n937, LD => DR_enable, Q => larray_5_9_port, QN => open); reg_reg_5_10_label : FDS2L port map( D => larray355_5_10_port, CP => clk, CR => n938, LD => DR_enable, Q => larray_5_10_port, QN => open); reg_reg_5_11_label : FDS2L port map( D => larray355_5_11_port, CP => clk, CR => n939, LD => DR_enable, Q => larray_5_11_port, QN => open); reg_reg_5_12_label : FDS2L port map( D => larray355_5_12_port, CP => clk, CR => n940, LD => DR_enable, Q => larray_5_12_port, QN => open); reg_reg_5_13_label : FDS2L port map( D => larray355_5_13_port, CP => clk, CR => n941, LD => DR_enable, Q => larray_5_13_port, QN => open); reg_reg_5_14_label : FDS2L port map( D => larray355_5_14_port, CP => clk, CR => n942, LD => DR_enable, Q => larray_5_14_port, QN => open); reg_reg_5_15_label : FDS2L port map( D => larray355_5_15_port, CP => clk, CR => n943, LD => DR_enable, Q => larray_5_15_port, QN => open); reg_reg_4_0_label : FDS2L port map( D => larray355_4_0_port, CP => clk, CR => n944, LD => DR_enable, Q => larray_4_0_port, QN => open); reg_reg_4_1_label : FDS2L port map( D => larray355_4_1_port, CP => clk, CR => n945, LD => DR_enable, Q => larray_4_1_port, QN => open); reg_reg_4_2_label : FDS2L port map( D => larray355_4_2_port, CP => clk, CR => n946, LD => DR_enable, Q => larray_4_2_port, QN => open); reg_reg_4_3_label : FDS2L port map( D => larray355_4_3_port, CP => clk, CR => n947, LD => DR_enable, Q => larray_4_3_port, QN => open); reg_reg_4_4_label : FDS2L port map( D => larray355_4_4_port, CP => clk, CR => n948, LD => DR_enable, Q => larray_4_4_port, QN => open); reg_reg_4_5_label : FDS2L port map( D => larray355_4_5_port, CP => clk, CR => n949, LD => DR_enable, Q => larray_4_5_port, QN => open); reg_reg_4_6_label : FDS2L port map( D => larray355_4_6_port, CP => clk, CR => n950, LD => DR_enable, Q => larray_4_6_port, QN => open); reg_reg_4_7_label : FDS2L port map( D => larray355_4_7_port, CP => clk, CR => n951, LD => DR_enable, Q => larray_4_7_port, QN => open); reg_reg_4_8_label : FDS2L port map( D => larray355_4_8_port, CP => clk, CR => n952, LD => DR_enable, Q => larray_4_8_port, QN => open); reg_reg_4_9_label : FDS2L port map( D => larray355_4_9_port, CP => clk, CR => n953, LD => DR_enable, Q => larray_4_9_port, QN => open); reg_reg_4_10_label : FDS2L port map( D => larray355_4_10_port, CP => clk, CR => n954, LD => DR_enable, Q => larray_4_10_port, QN => open); reg_reg_4_11_label : FDS2L port map( D => larray355_4_11_port, CP => clk, CR => n955, LD => DR_enable, Q => larray_4_11_port, QN => open); reg_reg_4_12_label : FDS2L port map( D => larray355_4_12_port, CP => clk, CR => n956, LD => DR_enable, Q => larray_4_12_port, QN => open); reg_reg_4_13_label : FDS2L port map( D => larray355_4_13_port, CP => clk, CR => n957, LD => DR_enable, Q => larray_4_13_port, QN => open); reg_reg_4_14_label : FDS2L port map( D => larray355_4_14_port, CP => clk, CR => n958, LD => DR_enable, Q => larray_4_14_port, QN => open); reg_reg_4_15_label : FDS2L port map( D => larray355_4_15_port, CP => clk, CR => n959, LD => DR_enable, Q => larray_4_15_port, QN => open); reg_reg_3_0_label : FDS2L port map( D => larray355_3_0_port, CP => clk, CR => n960, LD => DR_enable, Q => larray_3_0_port, QN => open); reg_reg_3_1_label : FDS2L port map( D => larray355_3_1_port, CP => clk, CR => n961, LD => DR_enable, Q => larray_3_1_port, QN => open); reg_reg_3_2_label : FDS2L port map( D => larray355_3_2_port, CP => clk, CR => n962, LD => DR_enable, Q => larray_3_2_port, QN => open); reg_reg_3_3_label : FDS2L port map( D => larray355_3_3_port, CP => clk, CR => n963, LD => DR_enable, Q => larray_3_3_port, QN => open); reg_reg_3_4_label : FDS2L port map( D => larray355_3_4_port, CP => clk, CR => n964, LD => DR_enable, Q => larray_3_4_port, QN => open); reg_reg_3_5_label : FDS2L port map( D => larray355_3_5_port, CP => clk, CR => n965, LD => DR_enable, Q => larray_3_5_port, QN => open); reg_reg_3_6_label : FDS2L port map( D => larray355_3_6_port, CP => clk, CR => n966, LD => DR_enable, Q => larray_3_6_port, QN => open); reg_reg_3_7_label : FDS2L port map( D => larray355_3_7_port, CP => clk, CR => n967, LD => DR_enable, Q => larray_3_7_port, QN => open); reg_reg_3_8_label : FDS2L port map( D => larray355_3_8_port, CP => clk, CR => n968, LD => DR_enable, Q => larray_3_8_port, QN => open); reg_reg_3_9_label : FDS2L port map( D => larray355_3_9_port, CP => clk, CR => n969, LD => DR_enable, Q => larray_3_9_port, QN => open); reg_reg_3_10_label : FDS2L port map( D => larray355_3_10_port, CP => clk, CR => n970, LD => DR_enable, Q => larray_3_10_port, QN => open); reg_reg_3_11_label : FDS2L port map( D => larray355_3_11_port, CP => clk, CR => n971, LD => DR_enable, Q => larray_3_11_port, QN => open); reg_reg_3_12_label : FDS2L port map( D => larray355_3_12_port, CP => clk, CR => n972, LD => DR_enable, Q => larray_3_12_port, QN => open); reg_reg_3_13_label : FDS2L port map( D => larray355_3_13_port, CP => clk, CR => n973, LD => DR_enable, Q => larray_3_13_port, QN => open); reg_reg_3_14_label : FDS2L port map( D => larray355_3_14_port, CP => clk, CR => n974, LD => DR_enable, Q => larray_3_14_port, QN => open); reg_reg_3_15_label : FDS2L port map( D => larray355_3_15_port, CP => clk, CR => n975, LD => DR_enable, Q => larray_3_15_port, QN => open); reg_reg_2_0_label : FDS2L port map( D => larray355_2_0_port, CP => clk, CR => n976, LD => DR_enable, Q => larray_2_0_port, QN => open); reg_reg_2_1_label : FDS2L port map( D => larray355_2_1_port, CP => clk, CR => n977, LD => DR_enable, Q => larray_2_1_port, QN => open); reg_reg_2_2_label : FDS2L port map( D => larray355_2_2_port, CP => clk, CR => n978, LD => DR_enable, Q => larray_2_2_port, QN => open); reg_reg_2_3_label : FDS2L port map( D => larray355_2_3_port, CP => clk, CR => n979, LD => DR_enable, Q => larray_2_3_port, QN => open); reg_reg_2_4_label : FDS2L port map( D => larray355_2_4_port, CP => clk, CR => n980, LD => DR_enable, Q => larray_2_4_port, QN => open); reg_reg_2_5_label : FDS2L port map( D => larray355_2_5_port, CP => clk, CR => n981, LD => DR_enable, Q => larray_2_5_port, QN => open); reg_reg_2_6_label : FDS2L port map( D => larray355_2_6_port, CP => clk, CR => n982, LD => DR_enable, Q => larray_2_6_port, QN => open); reg_reg_2_7_label : FDS2L port map( D => larray355_2_7_port, CP => clk, CR => n983, LD => DR_enable, Q => larray_2_7_port, QN => open); reg_reg_2_8_label : FDS2L port map( D => larray355_2_8_port, CP => clk, CR => n984, LD => DR_enable, Q => larray_2_8_port, QN => open); reg_reg_2_9_label : FDS2L port map( D => larray355_2_9_port, CP => clk, CR => n985, LD => DR_enable, Q => larray_2_9_port, QN => open); reg_reg_2_10_label : FDS2L port map( D => larray355_2_10_port, CP => clk, CR => n986, LD => DR_enable, Q => larray_2_10_port, QN => open); reg_reg_2_11_label : FDS2L port map( D => larray355_2_11_port, CP => clk, CR => n987, LD => DR_enable, Q => larray_2_11_port, QN => open); reg_reg_2_12_label : FDS2L port map( D => larray355_2_12_port, CP => clk, CR => n988, LD => DR_enable, Q => larray_2_12_port, QN => open); reg_reg_2_13_label : FDS2L port map( D => larray355_2_13_port, CP => clk, CR => n989, LD => DR_enable, Q => larray_2_13_port, QN => open); reg_reg_2_14_label : FDS2L port map( D => larray355_2_14_port, CP => clk, CR => n990, LD => DR_enable, Q => larray_2_14_port, QN => open); reg_reg_2_15_label : FDS2L port map( D => larray355_2_15_port, CP => clk, CR => n991, LD => DR_enable, Q => larray_2_15_port, QN => open); reg_reg_1_0_label : FDS2L port map( D => larray355_1_0_port, CP => clk, CR => n992, LD => DR_enable, Q => larray_1_0_port, QN => open); reg_reg_1_1_label : FDS2L port map( D => larray355_1_1_port, CP => clk, CR => n993, LD => DR_enable, Q => larray_1_1_port, QN => open); reg_reg_1_2_label : FDS2L port map( D => larray355_1_2_port, CP => clk, CR => n994, LD => DR_enable, Q => larray_1_2_port, QN => open); reg_reg_1_3_label : FDS2L port map( D => larray355_1_3_port, CP => clk, CR => n995, LD => DR_enable, Q => larray_1_3_port, QN => open); reg_reg_1_4_label : FDS2L port map( D => larray355_1_4_port, CP => clk, CR => n996, LD => DR_enable, Q => larray_1_4_port, QN => open); reg_reg_1_5_label : FDS2L port map( D => larray355_1_5_port, CP => clk, CR => n997, LD => DR_enable, Q => larray_1_5_port, QN => open); reg_reg_1_6_label : FDS2L port map( D => larray355_1_6_port, CP => clk, CR => n998, LD => DR_enable, Q => larray_1_6_port, QN => open); reg_reg_1_7_label : FDS2L port map( D => larray355_1_7_port, CP => clk, CR => n999, LD => DR_enable, Q => larray_1_7_port, QN => open); reg_reg_1_8_label : FDS2L port map( D => larray355_1_8_port, CP => clk, CR => n1000, LD => DR_enable, Q => larray_1_8_port, QN => open); reg_reg_1_9_label : FDS2L port map( D => larray355_1_9_port, CP => clk, CR => n1001, LD => DR_enable, Q => larray_1_9_port, QN => open); reg_reg_1_10_label : FDS2L port map( D => larray355_1_10_port, CP => clk, CR => n1002, LD => DR_enable, Q => larray_1_10_port, QN => open); reg_reg_1_11_label : FDS2L port map( D => larray355_1_11_port, CP => clk, CR => n1003, LD => DR_enable, Q => larray_1_11_port, QN => open); reg_reg_1_12_label : FDS2L port map( D => larray355_1_12_port, CP => clk, CR => n1004, LD => DR_enable, Q => larray_1_12_port, QN => open); reg_reg_1_13_label : FDS2L port map( D => larray355_1_13_port, CP => clk, CR => n1005, LD => DR_enable, Q => larray_1_13_port, QN => open); reg_reg_1_14_label : FDS2L port map( D => larray355_1_14_port, CP => clk, CR => n1006, LD => DR_enable, Q => larray_1_14_port, QN => open); reg_reg_1_15_label : FDS2L port map( D => larray355_1_15_port, CP => clk, CR => n1007, LD => DR_enable, Q => larray_1_15_port, QN => open); reg_reg_0_0_label : FDS2L port map( D => larray355_0_0_port, CP => clk, CR => n1008, LD => DR_enable, Q => larray_0_0_port, QN => open); reg_reg_0_1_label : FDS2L port map( D => larray355_0_1_port, CP => clk, CR => n1009, LD => DR_enable, Q => larray_0_1_port, QN => open); reg_reg_0_2_label : FDS2L port map( D => larray355_0_2_port, CP => clk, CR => n1010, LD => DR_enable, Q => larray_0_2_port, QN => open); reg_reg_0_3_label : FDS2L port map( D => larray355_0_3_port, CP => clk, CR => n1011, LD => DR_enable, Q => larray_0_3_port, QN => open); reg_reg_0_4_label : FDS2L port map( D => larray355_0_4_port, CP => clk, CR => n1012, LD => DR_enable, Q => larray_0_4_port, QN => open); reg_reg_0_5_label : FDS2L port map( D => larray355_0_5_port, CP => clk, CR => n1013, LD => DR_enable, Q => larray_0_5_port, QN => open); reg_reg_0_6_label : FDS2L port map( D => larray355_0_6_port, CP => clk, CR => n1014, LD => DR_enable, Q => larray_0_6_port, QN => open); reg_reg_0_7_label : FDS2L port map( D => larray355_0_7_port, CP => clk, CR => n1015, LD => DR_enable, Q => larray_0_7_port, QN => open); reg_reg_0_8_label : FDS2L port map( D => larray355_0_8_port, CP => clk, CR => n1016, LD => DR_enable, Q => larray_0_8_port, QN => open); reg_reg_0_9_label : FDS2L port map( D => larray355_0_9_port, CP => clk, CR => n1017, LD => DR_enable, Q => larray_0_9_port, QN => open); reg_reg_0_10_label : FDS2L port map( D => larray355_0_10_port, CP => clk, CR => n1018, LD => DR_enable, Q => larray_0_10_port, QN => open); reg_reg_0_11_label : FDS2L port map( D => larray355_0_11_port, CP => clk, CR => n1019, LD => DR_enable, Q => larray_0_11_port, QN => open); reg_reg_0_12_label : FDS2L port map( D => larray355_0_12_port, CP => clk, CR => n1020, LD => DR_enable, Q => larray_0_12_port, QN => open); reg_reg_0_13_label : FDS2L port map( D => larray355_0_13_port, CP => clk, CR => n1021, LD => DR_enable, Q => larray_0_13_port, QN => open); reg_reg_0_14_label : FDS2L port map( D => larray355_0_14_port, CP => clk, CR => n1022, LD => DR_enable, Q => larray_0_14_port, QN => open); reg_reg_0_15_label : FDS2L port map( D => larray355_0_15_port, CP => clk, CR => n1023, LD => DR_enable, Q => larray_0_15_port, QN => open); U54 : ND4 port map( A => n602, B => n603, C => n604, D => n605, Z => member46_15_port); U55 : ND4 port map( A => n606, B => n607, C => n608, D => n609, Z => member46_14_port); U56 : ND4 port map( A => n610, B => n611, C => n612, D => n613, Z => member46_13_port); U57 : ND4 port map( A => n614, B => n615, C => n616, D => n617, Z => member46_12_port); U58 : ND4 port map( A => n618, B => n619, C => n620, D => n621, Z => member46_11_port); U59 : ND4 port map( A => n622, B => n623, C => n624, D => n625, Z => member46_10_port); U60 : ND4 port map( A => n626, B => n627, C => n628, D => n629, Z => member46_9_port); U61 : ND4 port map( A => n630, B => n631, C => n632, D => n633, Z => member46_8_port); U62 : ND4 port map( A => n634, B => n635, C => n636, D => n637, Z => member46_7_port); U63 : ND4 port map( A => n638, B => n639, C => n640, D => n641, Z => member46_6_port); U64 : ND4 port map( A => n642, B => n643, C => n644, D => n645, Z => member46_5_port); U65 : ND4 port map( A => n646, B => n647, C => n648, D => n649, Z => member46_4_port); U66 : ND4 port map( A => n650, B => n651, C => n652, D => n653, Z => member46_3_port); U67 : ND4 port map( A => n654, B => n655, C => n656, D => n657, Z => member46_2_port); U68 : ND4 port map( A => n658, B => n659, C => n660, D => n661, Z => member46_1_port); U69 : ND4 port map( A => n662, B => n663, C => n664, D => n665, Z => member46_0_port); U70 : ND4 port map( A => n666, B => n667, C => n668, D => n669, Z => member185_15_port); U71 : ND4 port map( A => n670, B => n671, C => n672, D => n673, Z => member185_14_port); U72 : ND4 port map( A => n674, B => n675, C => n676, D => n677, Z => member185_13_port); U73 : ND4 port map( A => n678, B => n679, C => n680, D => n681, Z => member185_12_port); U74 : ND4 port map( A => n682, B => n683, C => n684, D => n685, Z => member185_11_port); U75 : ND4 port map( A => n686, B => n687, C => n688, D => n689, Z => member185_10_port); U76 : ND4 port map( A => n690, B => n691, C => n692, D => n693, Z => member185_9_port); U77 : ND4 port map( A => n694, B => n695, C => n696, D => n697, Z => member185_8_port); U78 : ND4 port map( A => n698, B => n699, C => n700, D => n701, Z => member185_7_port); U79 : ND4 port map( A => n702, B => n703, C => n704, D => n705, Z => member185_6_port); U80 : ND4 port map( A => n706, B => n707, C => n708, D => n709, Z => member185_5_port); U81 : ND4 port map( A => n710, B => n711, C => n712, D => n713, Z => member185_4_port); U82 : ND4 port map( A => n714, B => n715, C => n716, D => n717, Z => member185_3_port); U83 : ND4 port map( A => n718, B => n719, C => n720, D => n721, Z => member185_2_port); U84 : ND4 port map( A => n722, B => n723, C => n724, D => n725, Z => member185_1_port); U85 : ND4 port map( A => n726, B => n727, C => n728, D => n729, Z => member185_0_port); U86 : IV port map( A => SR1_address(1), Z => n730); U87 : IV port map( A => SR1_address(2), Z => n731); U88 : AN3 port map( A => SR1_address(2), B => SR1_address(1), C => SR1_address(0), Z => n732); U89 : AN3 port map( A => SR1_address(1), B => n731, C => SR1_address(0), Z => n733); U90 : AN3 port map( A => SR1_address(2), B => n730, C => SR1_address(0), Z => n734); U91 : AN3 port map( A => n730, B => n731, C => SR1_address(0), Z => n735); U92 : NR3 port map( A => n730, B => SR1_address(0), C => n731, Z => n736); U93 : NR3 port map( A => SR1_address(2), B => SR1_address(0), C => n730, Z => n737); U94 : NR3 port map( A => SR1_address(1), B => SR1_address(0), C => n731, Z => n738); U95 : NR3 port map( A => SR1_address(0), B => SR1_address(2), C => SR1_address(1), Z => n739); U96 : IV port map( A => SR2_address(2), Z => n740); U97 : IV port map( A => SR2_address(1), Z => n741); U98 : AN3 port map( A => SR2_address(0), B => SR2_address(2), C => SR2_address(1), Z => n742); U99 : AN3 port map( A => SR2_address(0), B => n740, C => SR2_address(1), Z => n743); U100 : AN3 port map( A => SR2_address(2), B => n741, C => SR2_address(0), Z => n744); U101 : AN3 port map( A => n740, B => n741, C => SR2_address(0), Z => n745); U102 : NR3 port map( A => n740, B => SR2_address(0), C => n741, Z => n746); U103 : NR3 port map( A => SR2_address(2), B => SR2_address(0), C => n741, Z => n747); U104 : NR3 port map( A => SR2_address(0), B => SR2_address(1), C => n740, Z => n748); U105 : NR3 port map( A => SR2_address(1), B => SR2_address(0), C => SR2_address(2), Z => n749); U106 : IV port map( A => DR_address(1), Z => n750); U107 : IV port map( A => DR_address(2), Z => n751); U108 : AO2 port map( A => larray_7_9_port, B => n753, C => data_in(6), D => n754, Z => n752); U109 : AO2 port map( A => larray_7_8_port, B => n753, C => data_in(7), D => n754, Z => n755); U110 : AO2 port map( A => larray_7_7_port, B => n753, C => data_in(8), D => n754, Z => n756); U111 : AO2 port map( A => larray_7_6_port, B => n753, C => data_in(9), D => n754, Z => n757); U112 : AO2 port map( A => larray_7_5_port, B => n753, C => data_in(10), D => n754, Z => n758); U113 : AO2 port map( A => larray_7_4_port, B => n753, C => data_in(11), D => n754, Z => n759); U114 : AO2 port map( A => larray_7_3_port, B => n753, C => data_in(12), D => n754, Z => n760); U115 : AO2 port map( A => larray_7_2_port, B => n753, C => data_in(13), D => n754, Z => n761); U116 : AO2 port map( A => larray_7_1_port, B => n753, C => data_in(14), D => n754, Z => n762); U117 : AO2 port map( A => larray_7_15_port, B => n753, C => data_in(0), D => n754, Z => n763); U118 : AO2 port map( A => larray_7_14_port, B => n753, C => data_in(1), D => n754, Z => n764); U119 : AO2 port map( A => larray_7_13_port, B => n753, C => data_in(2), D => n754, Z => n765); U120 : AO2 port map( A => larray_7_12_port, B => n753, C => data_in(3), D => n754, Z => n766); U121 : AO2 port map( A => larray_7_11_port, B => n753, C => data_in(4), D => n754, Z => n767); U122 : AO2 port map( A => larray_7_10_port, B => n753, C => data_in(5), D => n754, Z => n768); U123 : AO2 port map( A => larray_7_0_port, B => n753, C => data_in(15), D => n754, Z => n769); U124 : AO2 port map( A => larray_6_9_port, B => n771, C => data_in(6), D => n772, Z => n770); U125 : AO2 port map( A => larray_6_8_port, B => n771, C => data_in(7), D => n772, Z => n773); U126 : AO2 port map( A => larray_6_7_port, B => n771, C => data_in(8), D => n772, Z => n774); U127 : AO2 port map( A => larray_6_6_port, B => n771, C => data_in(9), D => n772, Z => n775); U128 : AO2 port map( A => larray_6_5_port, B => n771, C => data_in(10), D => n772, Z => n776); U129 : AO2 port map( A => larray_6_4_port, B => n771, C => data_in(11), D => n772, Z => n777); U130 : AO2 port map( A => larray_6_3_port, B => n771, C => data_in(12), D => n772, Z => n778); U131 : AO2 port map( A => larray_6_2_port, B => n771, C => data_in(13), D => n772, Z => n779); U132 : AO2 port map( A => larray_6_1_port, B => n771, C => data_in(14), D => n772, Z => n780); U133 : AO2 port map( A => larray_6_15_port, B => n771, C => data_in(0), D => n772, Z => n781); U134 : AO2 port map( A => larray_6_14_port, B => n771, C => data_in(1), D => n772, Z => n782); U135 : AO2 port map( A => larray_6_13_port, B => n771, C => data_in(2), D => n772, Z => n783); U136 : AO2 port map( A => larray_6_12_port, B => n771, C => data_in(3), D => n772, Z => n784); U137 : AO2 port map( A => larray_6_11_port, B => n771, C => data_in(4), D => n772, Z => n785); U138 : AO2 port map( A => larray_6_10_port, B => n771, C => data_in(5), D => n772, Z => n786); U139 : AO2 port map( A => larray_6_0_port, B => n771, C => data_in(15), D => n772, Z => n787); U140 : AO2 port map( A => larray_5_9_port, B => n789, C => data_in(6), D => n790, Z => n788); U141 : AO2 port map( A => larray_5_8_port, B => n789, C => data_in(7), D => n790, Z => n791); U142 : AO2 port map( A => larray_5_7_port, B => n789, C => data_in(8), D => n790, Z => n792); U143 : AO2 port map( A => larray_5_6_port, B => n789, C => data_in(9), D => n790, Z => n793); U144 : AO2 port map( A => larray_5_5_port, B => n789, C => data_in(10), D => n790, Z => n794); U145 : AO2 port map( A => larray_5_4_port, B => n789, C => data_in(11), D => n790, Z => n795); U146 : AO2 port map( A => larray_5_3_port, B => n789, C => data_in(12), D => n790, Z => n796); U147 : AO2 port map( A => larray_5_2_port, B => n789, C => data_in(13), D => n790, Z => n797); U148 : AO2 port map( A => larray_5_1_port, B => n789, C => data_in(14), D => n790, Z => n798); U149 : AO2 port map( A => larray_5_15_port, B => n789, C => data_in(0), D => n790, Z => n799); U150 : AO2 port map( A => larray_5_14_port, B => n789, C => data_in(1), D => n790, Z => n800); U151 : AO2 port map( A => larray_5_13_port, B => n789, C => data_in(2), D => n790, Z => n801); U152 : AO2 port map( A => larray_5_12_port, B => n789, C => data_in(3), D => n790, Z => n802); U153 : AO2 port map( A => larray_5_11_port, B => n789, C => data_in(4), D => n790, Z => n803); U154 : AO2 port map( A => larray_5_10_port, B => n789, C => data_in(5), D => n790, Z => n804); U155 : AO2 port map( A => larray_5_0_port, B => n789, C => data_in(15), D => n790, Z => n805); U156 : AO2 port map( A => larray_4_9_port, B => n807, C => data_in(6), D => n808, Z => n806); U157 : AO2 port map( A => larray_4_8_port, B => n807, C => data_in(7), D => n808, Z => n809); U158 : AO2 port map( A => larray_4_7_port, B => n807, C => data_in(8), D => n808, Z => n810); U159 : AO2 port map( A => larray_4_6_port, B => n807, C => data_in(9), D => n808, Z => n811); U160 : AO2 port map( A => larray_4_5_port, B => n807, C => data_in(10), D => n808, Z => n812); U161 : AO2 port map( A => larray_4_4_port, B => n807, C => data_in(11), D => n808, Z => n813); U162 : AO2 port map( A => larray_4_3_port, B => n807, C => data_in(12), D => n808, Z => n814); U163 : AO2 port map( A => larray_4_2_port, B => n807, C => data_in(13), D => n808, Z => n815); U164 : AO2 port map( A => larray_4_1_port, B => n807, C => data_in(14), D => n808, Z => n816); U165 : AO2 port map( A => larray_4_15_port, B => n807, C => data_in(0), D => n808, Z => n817); U166 : AO2 port map( A => larray_4_14_port, B => n807, C => data_in(1), D => n808, Z => n818); U167 : AO2 port map( A => larray_4_13_port, B => n807, C => data_in(2), D => n808, Z => n819); U168 : AO2 port map( A => larray_4_12_port, B => n807, C => data_in(3), D => n808, Z => n820); U169 : AO2 port map( A => larray_4_11_port, B => n807, C => data_in(4), D => n808, Z => n821); U170 : AO2 port map( A => larray_4_10_port, B => n807, C => data_in(5), D => n808, Z => n822); U171 : AO2 port map( A => larray_4_0_port, B => n807, C => data_in(15), D => n808, Z => n823); U172 : AO2 port map( A => larray_3_9_port, B => n825, C => data_in(6), D => n826, Z => n824); U173 : AO2 port map( A => larray_3_8_port, B => n825, C => data_in(7), D => n826, Z => n827); U174 : AO2 port map( A => larray_3_7_port, B => n825, C => data_in(8), D => n826, Z => n828); U175 : AO2 port map( A => larray_3_6_port, B => n825, C => data_in(9), D => n826, Z => n829); U176 : AO2 port map( A => larray_3_5_port, B => n825, C => data_in(10), D => n826, Z => n830); U177 : AO2 port map( A => larray_3_4_port, B => n825, C => data_in(11), D => n826, Z => n831); U178 : AO2 port map( A => larray_3_3_port, B => n825, C => data_in(12), D => n826, Z => n832); U179 : AO2 port map( A => larray_3_2_port, B => n825, C => data_in(13), D => n826, Z => n833); U180 : AO2 port map( A => larray_3_1_port, B => n825, C => data_in(14), D => n826, Z => n834); U181 : AO2 port map( A => larray_3_15_port, B => n825, C => data_in(0), D => n826, Z => n835); U182 : AO2 port map( A => larray_3_14_port, B => n825, C => data_in(1), D => n826, Z => n836); U183 : AO2 port map( A => larray_3_13_port, B => n825, C => data_in(2), D => n826, Z => n837); U184 : AO2 port map( A => larray_3_12_port, B => n825, C => data_in(3), D => n826, Z => n838); U185 : AO2 port map( A => larray_3_11_port, B => n825, C => data_in(4), D => n826, Z => n839); U186 : AO2 port map( A => larray_3_10_port, B => n825, C => data_in(5), D => n826, Z => n840); U187 : AO2 port map( A => larray_3_0_port, B => n825, C => data_in(15), D => n826, Z => n841); U188 : AO2 port map( A => larray_2_9_port, B => n843, C => data_in(6), D => n844, Z => n842); U189 : AO2 port map( A => larray_2_8_port, B => n843, C => data_in(7), D => n844, Z => n845); U190 : AO2 port map( A => larray_2_7_port, B => n843, C => data_in(8), D => n844, Z => n846); U191 : AO2 port map( A => larray_2_6_port, B => n843, C => data_in(9), D => n844, Z => n847); U192 : AO2 port map( A => larray_2_5_port, B => n843, C => data_in(10), D => n844, Z => n848); U193 : AO2 port map( A => larray_2_4_port, B => n843, C => data_in(11), D => n844, Z => n849); U194 : AO2 port map( A => larray_2_3_port, B => n843, C => data_in(12), D => n844, Z => n850); U195 : AO2 port map( A => larray_2_2_port, B => n843, C => data_in(13), D => n844, Z => n851); U196 : AO2 port map( A => larray_2_1_port, B => n843, C => data_in(14), D => n844, Z => n852); U197 : AO2 port map( A => larray_2_15_port, B => n843, C => data_in(0), D => n844, Z => n853); U198 : AO2 port map( A => larray_2_14_port, B => n843, C => data_in(1), D => n844, Z => n854); U199 : AO2 port map( A => larray_2_13_port, B => n843, C => data_in(2), D => n844, Z => n855); U200 : AO2 port map( A => larray_2_12_port, B => n843, C => data_in(3), D => n844, Z => n856); U201 : AO2 port map( A => larray_2_11_port, B => n843, C => data_in(4), D => n844, Z => n857); U202 : AO2 port map( A => larray_2_10_port, B => n843, C => data_in(5), D => n844, Z => n858); U203 : AO2 port map( A => larray_2_0_port, B => n843, C => data_in(15), D => n844, Z => n859); U204 : AO2 port map( A => larray_1_9_port, B => n861, C => data_in(6), D => n862, Z => n860); U205 : AO2 port map( A => larray_1_8_port, B => n861, C => data_in(7), D => n862, Z => n863); U206 : AO2 port map( A => larray_1_7_port, B => n861, C => data_in(8), D => n862, Z => n864); U207 : AO2 port map( A => larray_1_6_port, B => n861, C => data_in(9), D => n862, Z => n865); U208 : AO2 port map( A => larray_1_5_port, B => n861, C => data_in(10), D => n862, Z => n866); U209 : AO2 port map( A => larray_1_4_port, B => n861, C => data_in(11), D => n862, Z => n867); U210 : AO2 port map( A => larray_1_3_port, B => n861, C => data_in(12), D => n862, Z => n868); U211 : AO2 port map( A => larray_1_2_port, B => n861, C => data_in(13), D => n862, Z => n869); U212 : AO2 port map( A => larray_1_1_port, B => n861, C => data_in(14), D => n862, Z => n870); U213 : AO2 port map( A => larray_1_15_port, B => n861, C => data_in(0), D => n862, Z => n871); U214 : AO2 port map( A => larray_1_14_port, B => n861, C => data_in(1), D => n862, Z => n872); U215 : AO2 port map( A => larray_1_13_port, B => n861, C => data_in(2), D => n862, Z => n873); U216 : AO2 port map( A => larray_1_12_port, B => n861, C => data_in(3), D => n862, Z => n874); U217 : AO2 port map( A => larray_1_11_port, B => n861, C => data_in(4), D => n862, Z => n875); U218 : AO2 port map( A => larray_1_10_port, B => n861, C => data_in(5), D => n862, Z => n876); U219 : AO2 port map( A => larray_1_0_port, B => n861, C => data_in(15), D => n862, Z => n877); U220 : AO2 port map( A => larray_0_9_port, B => n879, C => data_in(6), D => n880, Z => n878); U221 : AO2 port map( A => larray_0_8_port, B => n879, C => data_in(7), D => n880, Z => n881); U222 : AO2 port map( A => larray_0_7_port, B => n879, C => data_in(8), D => n880, Z => n882); U223 : AO2 port map( A => larray_0_6_port, B => n879, C => data_in(9), D => n880, Z => n883); U224 : AO2 port map( A => larray_0_5_port, B => n879, C => data_in(10), D => n880, Z => n884); U225 : AO2 port map( A => larray_0_4_port, B => n879, C => data_in(11), D => n880, Z => n885); U226 : AO2 port map( A => larray_0_3_port, B => n879, C => data_in(12), D => n880, Z => n886); U227 : AO2 port map( A => larray_0_2_port, B => n879, C => data_in(13), D => n880, Z => n887); U228 : AO2 port map( A => larray_0_1_port, B => n879, C => data_in(14), D => n880, Z => n888); U229 : AO2 port map( A => larray_0_15_port, B => n879, C => data_in(0), D => n880, Z => n889); U230 : AO2 port map( A => larray_0_14_port, B => n879, C => data_in(1), D => n880, Z => n890); U231 : AO2 port map( A => larray_0_13_port, B => n879, C => data_in(2), D => n880, Z => n891); U232 : AO2 port map( A => larray_0_12_port, B => n879, C => data_in(3), D => n880, Z => n892); U233 : AO2 port map( A => larray_0_11_port, B => n879, C => data_in(4), D => n880, Z => n893); U234 : AO2 port map( A => larray_0_10_port, B => n879, C => data_in(5), D => n880, Z => n894); U235 : AO2 port map( A => larray_0_0_port, B => n879, C => data_in(15), D => n880, Z => n895); U236 : AO2 port map( A => n732, B => larray_7_9_port, C => n733, D => larray_6_9_port, Z => n629); U237 : AO2 port map( A => n734, B => larray_5_9_port, C => n735, D => larray_4_9_port, Z => n628); U238 : AO2 port map( A => n736, B => larray_3_9_port, C => n737, D => larray_2_9_port, Z => n627); U239 : AO2 port map( A => n738, B => larray_1_9_port, C => n739, D => larray_0_9_port, Z => n626); U240 : AO2 port map( A => larray_7_8_port, B => n732, C => larray_6_8_port, D => n733, Z => n633); U241 : AO2 port map( A => larray_5_8_port, B => n734, C => larray_4_8_port, D => n735, Z => n632); U242 : AO2 port map( A => larray_3_8_port, B => n736, C => larray_2_8_port, D => n737, Z => n631); U243 : AO2 port map( A => larray_1_8_port, B => n738, C => larray_0_8_port, D => n739, Z => n630); U244 : AO2 port map( A => larray_7_7_port, B => n732, C => larray_6_7_port, D => n733, Z => n637); U245 : AO2 port map( A => larray_5_7_port, B => n734, C => larray_4_7_port, D => n735, Z => n636); U246 : AO2 port map( A => larray_3_7_port, B => n736, C => larray_2_7_port, D => n737, Z => n635); U247 : AO2 port map( A => larray_1_7_port, B => n738, C => larray_0_7_port, D => n739, Z => n634); U248 : AO2 port map( A => larray_7_6_port, B => n732, C => larray_6_6_port, D => n733, Z => n641); U249 : AO2 port map( A => larray_5_6_port, B => n734, C => larray_4_6_port, D => n735, Z => n640); U250 : AO2 port map( A => larray_3_6_port, B => n736, C => larray_2_6_port, D => n737, Z => n639); U251 : AO2 port map( A => larray_1_6_port, B => n738, C => larray_0_6_port, D => n739, Z => n638); U252 : AO2 port map( A => larray_7_5_port, B => n732, C => larray_6_5_port, D => n733, Z => n645); U253 : AO2 port map( A => larray_5_5_port, B => n734, C => larray_4_5_port, D => n735, Z => n644); U254 : AO2 port map( A => larray_3_5_port, B => n736, C => larray_2_5_port, D => n737, Z => n643); U255 : AO2 port map( A => larray_1_5_port, B => n738, C => larray_0_5_port, D => n739, Z => n642); U256 : AO2 port map( A => larray_7_4_port, B => n732, C => larray_6_4_port, D => n733, Z => n649); U257 : AO2 port map( A => larray_5_4_port, B => n734, C => larray_4_4_port, D => n735, Z => n648); U258 : AO2 port map( A => larray_3_4_port, B => n736, C => larray_2_4_port, D => n737, Z => n647); U259 : AO2 port map( A => larray_1_4_port, B => n738, C => larray_0_4_port, D => n739, Z => n646); U260 : AO2 port map( A => larray_7_3_port, B => n732, C => larray_6_3_port, D => n733, Z => n653); U261 : AO2 port map( A => larray_5_3_port, B => n734, C => larray_4_3_port, D => n735, Z => n652); U262 : AO2 port map( A => larray_3_3_port, B => n736, C => larray_2_3_port, D => n737, Z => n651); U263 : AO2 port map( A => larray_1_3_port, B => n738, C => larray_0_3_port, D => n739, Z => n650); U264 : AO2 port map( A => larray_7_2_port, B => n732, C => larray_6_2_port, D => n733, Z => n657); U265 : AO2 port map( A => larray_5_2_port, B => n734, C => larray_4_2_port, D => n735, Z => n656); U266 : AO2 port map( A => larray_3_2_port, B => n736, C => larray_2_2_port, D => n737, Z => n655); U267 : AO2 port map( A => larray_1_2_port, B => n738, C => larray_0_2_port, D => n739, Z => n654); U268 : AO2 port map( A => larray_7_1_port, B => n732, C => larray_6_1_port, D => n733, Z => n661); U269 : AO2 port map( A => larray_5_1_port, B => n734, C => larray_4_1_port, D => n735, Z => n660); U270 : AO2 port map( A => larray_3_1_port, B => n736, C => larray_2_1_port, D => n737, Z => n659); U271 : AO2 port map( A => larray_1_1_port, B => n738, C => larray_0_1_port, D => n739, Z => n658); U272 : AO2 port map( A => larray_7_15_port, B => n732, C => larray_6_15_port , D => n733, Z => n605); U273 : AO2 port map( A => larray_5_15_port, B => n734, C => larray_4_15_port , D => n735, Z => n604); U274 : AO2 port map( A => larray_3_15_port, B => n736, C => larray_2_15_port , D => n737, Z => n603); U275 : AO2 port map( A => larray_1_15_port, B => n738, C => larray_0_15_port , D => n739, Z => n602); U276 : AO2 port map( A => larray_7_14_port, B => n732, C => larray_6_14_port , D => n733, Z => n609); U277 : AO2 port map( A => larray_5_14_port, B => n734, C => larray_4_14_port , D => n735, Z => n608); U278 : AO2 port map( A => larray_3_14_port, B => n736, C => larray_2_14_port , D => n737, Z => n607); U279 : AO2 port map( A => larray_1_14_port, B => n738, C => larray_0_14_port , D => n739, Z => n606); U280 : AO2 port map( A => larray_7_13_port, B => n732, C => larray_6_13_port , D => n733, Z => n613); U281 : AO2 port map( A => larray_5_13_port, B => n734, C => larray_4_13_port , D => n735, Z => n612); U282 : AO2 port map( A => larray_3_13_port, B => n736, C => larray_2_13_port , D => n737, Z => n611); U283 : AO2 port map( A => larray_1_13_port, B => n738, C => larray_0_13_port , D => n739, Z => n610); U284 : AO2 port map( A => larray_7_12_port, B => n732, C => larray_6_12_port , D => n733, Z => n617); U285 : AO2 port map( A => larray_5_12_port, B => n734, C => larray_4_12_port , D => n735, Z => n616); U286 : AO2 port map( A => larray_3_12_port, B => n736, C => larray_2_12_port , D => n737, Z => n615); U287 : AO2 port map( A => larray_1_12_port, B => n738, C => larray_0_12_port , D => n739, Z => n614); U288 : AO2 port map( A => larray_7_11_port, B => n732, C => larray_6_11_port , D => n733, Z => n621); U289 : AO2 port map( A => larray_5_11_port, B => n734, C => larray_4_11_port , D => n735, Z => n620); U290 : AO2 port map( A => larray_3_11_port, B => n736, C => larray_2_11_port , D => n737, Z => n619); U291 : AO2 port map( A => larray_1_11_port, B => n738, C => larray_0_11_port , D => n739, Z => n618); U292 : AO2 port map( A => larray_7_10_port, B => n732, C => larray_6_10_port , D => n733, Z => n625); U293 : AO2 port map( A => larray_5_10_port, B => n734, C => larray_4_10_port , D => n735, Z => n624); U294 : AO2 port map( A => larray_3_10_port, B => n736, C => larray_2_10_port , D => n737, Z => n623); U295 : AO2 port map( A => larray_1_10_port, B => n738, C => larray_0_10_port , D => n739, Z => n622); U296 : AO2 port map( A => larray_7_0_port, B => n732, C => larray_6_0_port, D => n733, Z => n665); U297 : AO2 port map( A => larray_5_0_port, B => n734, C => larray_4_0_port, D => n735, Z => n664); U298 : AO2 port map( A => larray_3_0_port, B => n736, C => larray_2_0_port, D => n737, Z => n663); U299 : AO2 port map( A => larray_1_0_port, B => n738, C => larray_0_0_port, D => n739, Z => n662); U300 : AO2 port map( A => n742, B => larray_7_9_port, C => n743, D => larray_6_9_port, Z => n693); U301 : AO2 port map( A => n744, B => larray_5_9_port, C => n745, D => larray_4_9_port, Z => n692); U302 : AO2 port map( A => n746, B => larray_3_9_port, C => n747, D => larray_2_9_port, Z => n691); U303 : AO2 port map( A => n748, B => larray_1_9_port, C => n749, D => larray_0_9_port, Z => n690); U304 : AO2 port map( A => n742, B => larray_7_8_port, C => n743, D => larray_6_8_port, Z => n697); U305 : AO2 port map( A => n744, B => larray_5_8_port, C => n745, D => larray_4_8_port, Z => n696); U306 : AO2 port map( A => n746, B => larray_3_8_port, C => n747, D => larray_2_8_port, Z => n695); U307 : AO2 port map( A => n748, B => larray_1_8_port, C => n749, D => larray_0_8_port, Z => n694); U308 : AO2 port map( A => n742, B => larray_7_7_port, C => n743, D => larray_6_7_port, Z => n701); U309 : AO2 port map( A => n744, B => larray_5_7_port, C => n745, D => larray_4_7_port, Z => n700); U310 : AO2 port map( A => n746, B => larray_3_7_port, C => n747, D => larray_2_7_port, Z => n699); U311 : AO2 port map( A => n748, B => larray_1_7_port, C => n749, D => larray_0_7_port, Z => n698); U312 : AO2 port map( A => n742, B => larray_7_6_port, C => n743, D => larray_6_6_port, Z => n705); U313 : AO2 port map( A => n744, B => larray_5_6_port, C => n745, D => larray_4_6_port, Z => n704); U314 : AO2 port map( A => n746, B => larray_3_6_port, C => n747, D => larray_2_6_port, Z => n703); U315 : AO2 port map( A => n748, B => larray_1_6_port, C => n749, D => larray_0_6_port, Z => n702); U316 : AO2 port map( A => n742, B => larray_7_5_port, C => n743, D => larray_6_5_port, Z => n709); U317 : AO2 port map( A => n744, B => larray_5_5_port, C => n745, D => larray_4_5_port, Z => n708); U318 : AO2 port map( A => n746, B => larray_3_5_port, C => n747, D => larray_2_5_port, Z => n707); U319 : AO2 port map( A => n748, B => larray_1_5_port, C => n749, D => larray_0_5_port, Z => n706); U320 : AO2 port map( A => n742, B => larray_7_4_port, C => n743, D => larray_6_4_port, Z => n713); U321 : AO2 port map( A => n744, B => larray_5_4_port, C => n745, D => larray_4_4_port, Z => n712); U322 : AO2 port map( A => n746, B => larray_3_4_port, C => n747, D => larray_2_4_port, Z => n711); U323 : AO2 port map( A => n748, B => larray_1_4_port, C => n749, D => larray_0_4_port, Z => n710); U324 : AO2 port map( A => n742, B => larray_7_3_port, C => n743, D => larray_6_3_port, Z => n717); U325 : AO2 port map( A => n744, B => larray_5_3_port, C => n745, D => larray_4_3_port, Z => n716); U326 : AO2 port map( A => n746, B => larray_3_3_port, C => n747, D => larray_2_3_port, Z => n715); U327 : AO2 port map( A => n748, B => larray_1_3_port, C => n749, D => larray_0_3_port, Z => n714); U328 : AO2 port map( A => n742, B => larray_7_2_port, C => n743, D => larray_6_2_port, Z => n721); U329 : AO2 port map( A => n744, B => larray_5_2_port, C => n745, D => larray_4_2_port, Z => n720); U330 : AO2 port map( A => n746, B => larray_3_2_port, C => n747, D => larray_2_2_port, Z => n719); U331 : AO2 port map( A => n748, B => larray_1_2_port, C => n749, D => larray_0_2_port, Z => n718); U332 : AO2 port map( A => n742, B => larray_7_1_port, C => n743, D => larray_6_1_port, Z => n725); U333 : AO2 port map( A => n744, B => larray_5_1_port, C => n745, D => larray_4_1_port, Z => n724); U334 : AO2 port map( A => n746, B => larray_3_1_port, C => n747, D => larray_2_1_port, Z => n723); U335 : AO2 port map( A => n748, B => larray_1_1_port, C => n749, D => larray_0_1_port, Z => n722); U336 : AO2 port map( A => n742, B => larray_7_15_port, C => n743, D => larray_6_15_port, Z => n669); U337 : AO2 port map( A => n744, B => larray_5_15_port, C => n745, D => larray_4_15_port, Z => n668); U338 : AO2 port map( A => n746, B => larray_3_15_port, C => n747, D => larray_2_15_port, Z => n667); U339 : AO2 port map( A => n748, B => larray_1_15_port, C => n749, D => larray_0_15_port, Z => n666); U340 : AO2 port map( A => n742, B => larray_7_14_port, C => n743, D => larray_6_14_port, Z => n673); U341 : AO2 port map( A => n744, B => larray_5_14_port, C => n745, D => larray_4_14_port, Z => n672); U342 : AO2 port map( A => n746, B => larray_3_14_port, C => n747, D => larray_2_14_port, Z => n671); U343 : AO2 port map( A => n748, B => larray_1_14_port, C => n749, D => larray_0_14_port, Z => n670); U344 : AO2 port map( A => n742, B => larray_7_13_port, C => n743, D => larray_6_13_port, Z => n677); U345 : AO2 port map( A => n744, B => larray_5_13_port, C => n745, D => larray_4_13_port, Z => n676); U346 : AO2 port map( A => n746, B => larray_3_13_port, C => n747, D => larray_2_13_port, Z => n675); U347 : AO2 port map( A => n748, B => larray_1_13_port, C => n749, D => larray_0_13_port, Z => n674); U348 : AO2 port map( A => n742, B => larray_7_12_port, C => n743, D => larray_6_12_port, Z => n681); U349 : AO2 port map( A => n744, B => larray_5_12_port, C => n745, D => larray_4_12_port, Z => n680); U350 : AO2 port map( A => n746, B => larray_3_12_port, C => n747, D => larray_2_12_port, Z => n679); U351 : AO2 port map( A => n748, B => larray_1_12_port, C => n749, D => larray_0_12_port, Z => n678); U352 : AO2 port map( A => n742, B => larray_7_11_port, C => n743, D => larray_6_11_port, Z => n685); U353 : AO2 port map( A => n744, B => larray_5_11_port, C => n745, D => larray_4_11_port, Z => n684); U354 : AO2 port map( A => n746, B => larray_3_11_port, C => n747, D => larray_2_11_port, Z => n683); U355 : AO2 port map( A => n748, B => larray_1_11_port, C => n749, D => larray_0_11_port, Z => n682); U356 : AO2 port map( A => n742, B => larray_7_10_port, C => n743, D => larray_6_10_port, Z => n689); U357 : AO2 port map( A => n744, B => larray_5_10_port, C => n745, D => larray_4_10_port, Z => n688); U358 : AO2 port map( A => n746, B => larray_3_10_port, C => n747, D => larray_2_10_port, Z => n687); U359 : AO2 port map( A => n748, B => larray_1_10_port, C => n749, D => larray_0_10_port, Z => n686); U360 : AO2 port map( A => n742, B => larray_7_0_port, C => n743, D => larray_6_0_port, Z => n729); U361 : AO2 port map( A => n744, B => larray_5_0_port, C => n745, D => larray_4_0_port, Z => n728); U362 : AO2 port map( A => n746, B => larray_3_0_port, C => n747, D => larray_2_0_port, Z => n727); U363 : AO2 port map( A => n748, B => larray_1_0_port, C => n749, D => larray_0_0_port, Z => n726); U364 : AN3 port map( A => n750, B => n751, C => DR_address(0), Z => n808); U365 : AN3 port map( A => DR_address(2), B => n750, C => DR_address(0), Z => n790); U366 : AN3 port map( A => DR_address(1), B => n751, C => DR_address(0), Z => n772); U367 : AN3 port map( A => DR_address(2), B => DR_address(1), C => DR_address(0), Z => n754); U368 : NR3 port map( A => DR_address(0), B => DR_address(2), C => DR_address(1), Z => n880); U369 : NR3 port map( A => DR_address(1), B => DR_address(0), C => n751, Z => n862); U370 : NR3 port map( A => DR_address(2), B => DR_address(0), C => n750, Z => n844); U371 : NR3 port map( A => n750, B => DR_address(0), C => n751, Z => n826); U372 : IV port map( A => n754, Z => n753); U373 : IV port map( A => n772, Z => n771); U374 : IV port map( A => n790, Z => n789); U375 : IV port map( A => n808, Z => n807); U376 : IV port map( A => n826, Z => n825); U377 : IV port map( A => n844, Z => n843); U378 : IV port map( A => n862, Z => n861); U379 : IV port map( A => n880, Z => n879); U380 : IV port map( A => n752, Z => larray355_7_9_port); U381 : IV port map( A => n755, Z => larray355_7_8_port); U382 : IV port map( A => n756, Z => larray355_7_7_port); U383 : IV port map( A => n757, Z => larray355_7_6_port); U384 : IV port map( A => n758, Z => larray355_7_5_port); U385 : IV port map( A => n759, Z => larray355_7_4_port); U386 : IV port map( A => n760, Z => larray355_7_3_port); U387 : IV port map( A => n761, Z => larray355_7_2_port); U388 : IV port map( A => n762, Z => larray355_7_1_port); U389 : IV port map( A => n763, Z => larray355_7_15_port); U390 : IV port map( A => n764, Z => larray355_7_14_port); U391 : IV port map( A => n765, Z => larray355_7_13_port); U392 : IV port map( A => n766, Z => larray355_7_12_port); U393 : IV port map( A => n767, Z => larray355_7_11_port); U394 : IV port map( A => n768, Z => larray355_7_10_port); U395 : IV port map( A => n769, Z => larray355_7_0_port); U396 : IV port map( A => n770, Z => larray355_6_9_port); U397 : IV port map( A => n773, Z => larray355_6_8_port); U398 : IV port map( A => n774, Z => larray355_6_7_port); U399 : IV port map( A => n775, Z => larray355_6_6_port); U400 : IV port map( A => n776, Z => larray355_6_5_port); U401 : IV port map( A => n777, Z => larray355_6_4_port); U402 : IV port map( A => n778, Z => larray355_6_3_port); U403 : IV port map( A => n779, Z => larray355_6_2_port); U404 : IV port map( A => n780, Z => larray355_6_1_port); U405 : IV port map( A => n781, Z => larray355_6_15_port); U406 : IV port map( A => n782, Z => larray355_6_14_port); U407 : IV port map( A => n783, Z => larray355_6_13_port); U408 : IV port map( A => n784, Z => larray355_6_12_port); U409 : IV port map( A => n785, Z => larray355_6_11_port); U410 : IV port map( A => n786, Z => larray355_6_10_port); U411 : IV port map( A => n787, Z => larray355_6_0_port); U412 : IV port map( A => n788, Z => larray355_5_9_port); U413 : IV port map( A => n791, Z => larray355_5_8_port); U414 : IV port map( A => n792, Z => larray355_5_7_port); U415 : IV port map( A => n793, Z => larray355_5_6_port); U416 : IV port map( A => n794, Z => larray355_5_5_port); U417 : IV port map( A => n795, Z => larray355_5_4_port); U418 : IV port map( A => n796, Z => larray355_5_3_port); U419 : IV port map( A => n797, Z => larray355_5_2_port); U420 : IV port map( A => n798, Z => larray355_5_1_port); U421 : IV port map( A => n799, Z => larray355_5_15_port); U422 : IV port map( A => n800, Z => larray355_5_14_port); U423 : IV port map( A => n801, Z => larray355_5_13_port); U424 : IV port map( A => n802, Z => larray355_5_12_port); U425 : IV port map( A => n803, Z => larray355_5_11_port); U426 : IV port map( A => n804, Z => larray355_5_10_port); U427 : IV port map( A => n805, Z => larray355_5_0_port); U428 : IV port map( A => n806, Z => larray355_4_9_port); U429 : IV port map( A => n809, Z => larray355_4_8_port); U430 : IV port map( A => n810, Z => larray355_4_7_port); U431 : IV port map( A => n811, Z => larray355_4_6_port); U432 : IV port map( A => n812, Z => larray355_4_5_port); U433 : IV port map( A => n813, Z => larray355_4_4_port); U434 : IV port map( A => n814, Z => larray355_4_3_port); U435 : IV port map( A => n815, Z => larray355_4_2_port); U436 : IV port map( A => n816, Z => larray355_4_1_port); U437 : IV port map( A => n817, Z => larray355_4_15_port); U438 : IV port map( A => n818, Z => larray355_4_14_port); U439 : IV port map( A => n819, Z => larray355_4_13_port); U440 : IV port map( A => n820, Z => larray355_4_12_port); U441 : IV port map( A => n821, Z => larray355_4_11_port); U442 : IV port map( A => n822, Z => larray355_4_10_port); U443 : IV port map( A => n823, Z => larray355_4_0_port); U444 : IV port map( A => n824, Z => larray355_3_9_port); U445 : IV port map( A => n827, Z => larray355_3_8_port); U446 : IV port map( A => n828, Z => larray355_3_7_port); U447 : IV port map( A => n829, Z => larray355_3_6_port); U448 : IV port map( A => n830, Z => larray355_3_5_port); U449 : IV port map( A => n831, Z => larray355_3_4_port); U450 : IV port map( A => n832, Z => larray355_3_3_port); U451 : IV port map( A => n833, Z => larray355_3_2_port); U452 : IV port map( A => n834, Z => larray355_3_1_port); U453 : IV port map( A => n835, Z => larray355_3_15_port); U454 : IV port map( A => n836, Z => larray355_3_14_port); U455 : IV port map( A => n837, Z => larray355_3_13_port); U456 : IV port map( A => n838, Z => larray355_3_12_port); U457 : IV port map( A => n839, Z => larray355_3_11_port); U458 : IV port map( A => n840, Z => larray355_3_10_port); U459 : IV port map( A => n841, Z => larray355_3_0_port); U460 : IV port map( A => n842, Z => larray355_2_9_port); U461 : IV port map( A => n845, Z => larray355_2_8_port); U462 : IV port map( A => n846, Z => larray355_2_7_port); U463 : IV port map( A => n847, Z => larray355_2_6_port); U464 : IV port map( A => n848, Z => larray355_2_5_port); U465 : IV port map( A => n849, Z => larray355_2_4_port); U466 : IV port map( A => n850, Z => larray355_2_3_port); U467 : IV port map( A => n851, Z => larray355_2_2_port); U468 : IV port map( A => n852, Z => larray355_2_1_port); U469 : IV port map( A => n853, Z => larray355_2_15_port); U470 : IV port map( A => n854, Z => larray355_2_14_port); U471 : IV port map( A => n855, Z => larray355_2_13_port); U472 : IV port map( A => n856, Z => larray355_2_12_port); U473 : IV port map( A => n857, Z => larray355_2_11_port); U474 : IV port map( A => n858, Z => larray355_2_10_port); U475 : IV port map( A => n859, Z => larray355_2_0_port); U476 : IV port map( A => n860, Z => larray355_1_9_port); U477 : IV port map( A => n863, Z => larray355_1_8_port); U478 : IV port map( A => n864, Z => larray355_1_7_port); U479 : IV port map( A => n865, Z => larray355_1_6_port); U480 : IV port map( A => n866, Z => larray355_1_5_port); U481 : IV port map( A => n867, Z => larray355_1_4_port); U482 : IV port map( A => n868, Z => larray355_1_3_port); U483 : IV port map( A => n869, Z => larray355_1_2_port); U484 : IV port map( A => n870, Z => larray355_1_1_port); U485 : IV port map( A => n871, Z => larray355_1_15_port); U486 : IV port map( A => n872, Z => larray355_1_14_port); U487 : IV port map( A => n873, Z => larray355_1_13_port); U488 : IV port map( A => n874, Z => larray355_1_12_port); U489 : IV port map( A => n875, Z => larray355_1_11_port); U490 : IV port map( A => n876, Z => larray355_1_10_port); U491 : IV port map( A => n877, Z => larray355_1_0_port); U492 : IV port map( A => n878, Z => larray355_0_9_port); U493 : IV port map( A => n881, Z => larray355_0_8_port); U494 : IV port map( A => n882, Z => larray355_0_7_port); U495 : IV port map( A => n883, Z => larray355_0_6_port); U496 : IV port map( A => n884, Z => larray355_0_5_port); U497 : IV port map( A => n885, Z => larray355_0_4_port); U498 : IV port map( A => n886, Z => larray355_0_3_port); U499 : IV port map( A => n887, Z => larray355_0_2_port); U500 : IV port map( A => n888, Z => larray355_0_1_port); U501 : IV port map( A => n889, Z => larray355_0_15_port); U502 : IV port map( A => n890, Z => larray355_0_14_port); U503 : IV port map( A => n891, Z => larray355_0_13_port); U504 : IV port map( A => n892, Z => larray355_0_12_port); U505 : IV port map( A => n893, Z => larray355_0_11_port); U506 : IV port map( A => n894, Z => larray355_0_10_port); U507 : IV port map( A => n895, Z => larray355_0_0_port); n896 <= '1'; n897 <= '1'; n898 <= '1'; n899 <= '1'; n900 <= '1'; n901 <= '1'; n902 <= '1'; n903 <= '1'; n904 <= '1'; n905 <= '1'; n906 <= '1'; n907 <= '1'; n908 <= '1'; n909 <= '1'; n910 <= '1'; n911 <= '1'; n912 <= '1'; n913 <= '1'; n914 <= '1'; n915 <= '1'; n916 <= '1'; n917 <= '1'; n918 <= '1'; n919 <= '1'; n920 <= '1'; n921 <= '1'; n922 <= '1'; n923 <= '1'; n924 <= '1'; n925 <= '1'; n926 <= '1'; n927 <= '1'; n928 <= '1'; n929 <= '1'; n930 <= '1'; n931 <= '1'; n932 <= '1'; n933 <= '1'; n934 <= '1'; n935 <= '1'; n936 <= '1'; n937 <= '1'; n938 <= '1'; n939 <= '1'; n940 <= '1'; n941 <= '1'; n942 <= '1'; n943 <= '1'; n944 <= '1'; n945 <= '1'; n946 <= '1'; n947 <= '1'; n948 <= '1'; n949 <= '1'; n950 <= '1'; n951 <= '1'; n952 <= '1'; n953 <= '1'; n954 <= '1'; n955 <= '1'; n956 <= '1'; n957 <= '1'; n958 <= '1'; n959 <= '1'; n960 <= '1'; n961 <= '1'; n962 <= '1'; n963 <= '1'; n964 <= '1'; n965 <= '1'; n966 <= '1'; n967 <= '1'; n968 <= '1'; n969 <= '1'; n970 <= '1'; n971 <= '1'; n972 <= '1'; n973 <= '1'; n974 <= '1'; n975 <= '1'; n976 <= '1'; n977 <= '1'; n978 <= '1'; n979 <= '1'; n980 <= '1'; n981 <= '1'; n982 <= '1'; n983 <= '1'; n984 <= '1'; n985 <= '1'; n986 <= '1'; n987 <= '1'; n988 <= '1'; n989 <= '1'; n990 <= '1'; n991 <= '1'; n992 <= '1'; n993 <= '1'; n994 <= '1'; n995 <= '1'; n996 <= '1'; n997 <= '1'; n998 <= '1'; n999 <= '1'; n1000 <= '1'; n1001 <= '1'; n1002 <= '1'; n1003 <= '1'; n1004 <= '1'; n1005 <= '1'; n1006 <= '1'; n1007 <= '1'; n1008 <= '1'; n1009 <= '1'; n1010 <= '1'; n1011 <= '1'; n1012 <= '1'; n1013 <= '1'; n1014 <= '1'; n1015 <= '1'; n1016 <= '1'; n1017 <= '1'; n1018 <= '1'; n1019 <= '1'; n1020 <= '1'; n1021 <= '1'; n1022 <= '1'; n1023 <= '1'; end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity LC2_ALU_DW01_add_16_0 is port( A, B : in std_logic_vector (0 to 15); CI : in std_logic; SUM : out std_logic_vector (0 to 15); CO : out std_logic); end LC2_ALU_DW01_add_16_0; architecture SYN of LC2_ALU_DW01_add_16_0 is component EO3P port( A, B, C : in std_logic; Z : out std_logic); end component; component FA1A port( CI, A, B : in std_logic; S, CO : out std_logic); end component; component AN2 port( A, B : in std_logic; Z : out std_logic); end component; component EO port( A, B : in std_logic; Z : out std_logic); end component; signal carry_9_port, carry_4_port, carry_2_port, carry_15_port, carry_13_port, carry_6_port, carry_14_port, carry_11_port, carry_10_port, carry_12_port, carry_8_port, carry_7_port, carry_3_port, carry_5_port, carry_1_port : std_logic; begin U1_15 : EO3P port map( A => A(0), B => B(0), C => carry_15_port, Z => SUM(0) ); U1_14 : FA1A port map( CI => carry_14_port, A => A(1), B => B(1), S => SUM(1), CO => carry_15_port); U1_13 : FA1A port map( CI => carry_13_port, A => A(2), B => B(2), S => SUM(2), CO => carry_14_port); U1_12 : FA1A port map( CI => carry_12_port, A => A(3), B => B(3), S => SUM(3), CO => carry_13_port); U1_11 : FA1A port map( CI => carry_11_port, A => A(4), B => B(4), S => SUM(4), CO => carry_12_port); U1_10 : FA1A port map( CI => carry_10_port, A => A(5), B => B(5), S => SUM(5), CO => carry_11_port); U1_9 : FA1A port map( CI => carry_9_port, A => A(6), B => B(6), S => SUM(6), CO => carry_10_port); U1_8 : FA1A port map( CI => carry_8_port, A => A(7), B => B(7), S => SUM(7), CO => carry_9_port); U1_7 : FA1A port map( CI => carry_7_port, A => A(8), B => B(8), S => SUM(8), CO => carry_8_port); U1_6 : FA1A port map( CI => carry_6_port, A => A(9), B => B(9), S => SUM(9), CO => carry_7_port); U1_5 : FA1A port map( CI => carry_5_port, A => A(10), B => B(10), S => SUM(10), CO => carry_6_port); U1_4 : FA1A port map( CI => carry_4_port, A => A(11), B => B(11), S => SUM(11), CO => carry_5_port); U1_3 : FA1A port map( CI => carry_3_port, A => A(12), B => B(12), S => SUM(12), CO => carry_4_port); U1_2 : FA1A port map( CI => carry_2_port, A => A(13), B => B(13), S => SUM(13), CO => carry_3_port); U1_1 : FA1A port map( CI => carry_1_port, A => A(14), B => B(14), S => SUM(14), CO => carry_2_port); U4 : AN2 port map( A => B(15), B => A(15), Z => carry_1_port); U5 : EO port map( A => A(15), B => B(15), Z => SUM(15)); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity LC2_ALU is port( A, B : in std_logic_vector (0 to 15); S : in std_logic_vector (0 to 1); O : out std_logic_vector (0 to 15)); end LC2_ALU; architecture SYN of LC2_ALU is component ND2 port( A, B : in std_logic; Z : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component AN2 port( A, B : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component LC2_ALU_DW01_add_16_0 port( A, B : in std_logic_vector (0 to 15); CI : in std_logic; SUM : out std_logic_vector (0 to 15); CO : out std_logic); end component; signal X_return86_13_port, X_return86_15_port, X_return86_11_port, X_return86_7_port, X_return86_3_port, X_return86_8_port, X_return86_1_port, X_return86_5_port, X_return86_4_port, X_return86_9_port, X_return86_0_port, X_return86_2_port, X_return86_6_port, X_return86_10_port, X_return86_14_port, X_return86_12_port, n599, n600, n601, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106 : std_logic; begin U26 : ND2 port map( A => n599, B => n600, Z => O(0)); U27 : ND2 port map( A => n601, B => n1024, Z => O(1)); U28 : ND2 port map( A => n1025, B => n1026, Z => O(2)); U29 : ND2 port map( A => n1027, B => n1028, Z => O(3)); U30 : ND2 port map( A => n1029, B => n1030, Z => O(4)); U31 : ND2 port map( A => n1031, B => n1032, Z => O(5)); U32 : ND2 port map( A => n1033, B => n1034, Z => O(6)); U33 : ND2 port map( A => n1035, B => n1036, Z => O(7)); U34 : ND2 port map( A => n1037, B => n1038, Z => O(8)); U35 : ND2 port map( A => n1039, B => n1040, Z => O(9)); U36 : ND2 port map( A => n1041, B => n1042, Z => O(10)); U37 : ND2 port map( A => n1043, B => n1044, Z => O(11)); U38 : ND2 port map( A => n1045, B => n1046, Z => O(12)); U39 : ND2 port map( A => n1047, B => n1048, Z => O(13)); U40 : ND2 port map( A => n1049, B => n1050, Z => O(14)); U41 : ND2 port map( A => n1051, B => n1052, Z => O(15)); U42 : NR2 port map( A => S(1), B => S(0), Z => n1053); U43 : IV port map( A => S(1), Z => n1054); U44 : NR2 port map( A => n1054, B => S(0), Z => n1055); U45 : ND2 port map( A => n1057, B => n1058, Z => n1056); U46 : ND2 port map( A => n1057, B => n1060, Z => n1059); U47 : ND2 port map( A => n1057, B => n1062, Z => n1061); U48 : ND2 port map( A => n1057, B => n1064, Z => n1063); U49 : ND2 port map( A => n1057, B => n1066, Z => n1065); U50 : ND2 port map( A => n1057, B => n1068, Z => n1067); U51 : ND2 port map( A => n1057, B => n1070, Z => n1069); U52 : ND2 port map( A => n1057, B => n1072, Z => n1071); U53 : ND2 port map( A => n1057, B => n1074, Z => n1073); U54 : ND2 port map( A => n1057, B => n1076, Z => n1075); U55 : ND2 port map( A => n1057, B => n1078, Z => n1077); U56 : ND2 port map( A => n1057, B => n1080, Z => n1079); U57 : ND2 port map( A => n1057, B => n1082, Z => n1081); U58 : ND2 port map( A => n1057, B => n1084, Z => n1083); U59 : ND2 port map( A => n1057, B => n1086, Z => n1085); U60 : ND2 port map( A => n1057, B => n1088, Z => n1087); U61 : ND2 port map( A => S(0), B => n1054, Z => n1057); U62 : AN2 port map( A => S(0), B => S(1), Z => n1089); U63 : ND2 port map( A => n1055, B => B(6), Z => n1058); U64 : ND2 port map( A => n1053, B => X_return86_9_port, Z => n1034); U65 : ND2 port map( A => B(7), B => n1055, Z => n1060); U66 : ND2 port map( A => X_return86_8_port, B => n1053, Z => n1036); U67 : ND2 port map( A => B(8), B => n1055, Z => n1062); U68 : ND2 port map( A => X_return86_7_port, B => n1053, Z => n1038); U69 : ND2 port map( A => B(9), B => n1055, Z => n1064); U70 : ND2 port map( A => X_return86_6_port, B => n1053, Z => n1040); U71 : ND2 port map( A => B(10), B => n1055, Z => n1066); U72 : ND2 port map( A => X_return86_5_port, B => n1053, Z => n1042); U73 : ND2 port map( A => B(11), B => n1055, Z => n1068); U74 : ND2 port map( A => X_return86_4_port, B => n1053, Z => n1044); U75 : ND2 port map( A => B(12), B => n1055, Z => n1070); U76 : ND2 port map( A => X_return86_3_port, B => n1053, Z => n1046); U77 : ND2 port map( A => B(13), B => n1055, Z => n1072); U78 : ND2 port map( A => X_return86_2_port, B => n1053, Z => n1048); U79 : ND2 port map( A => B(14), B => n1055, Z => n1074); U80 : ND2 port map( A => X_return86_1_port, B => n1053, Z => n1050); U81 : ND2 port map( A => B(0), B => n1055, Z => n1076); U82 : ND2 port map( A => X_return86_15_port, B => n1053, Z => n600); U83 : ND2 port map( A => B(1), B => n1055, Z => n1078); U84 : ND2 port map( A => X_return86_14_port, B => n1053, Z => n1024); U85 : ND2 port map( A => B(2), B => n1055, Z => n1080); U86 : ND2 port map( A => X_return86_13_port, B => n1053, Z => n1026); U87 : ND2 port map( A => B(3), B => n1055, Z => n1082); U88 : ND2 port map( A => X_return86_12_port, B => n1053, Z => n1028); U89 : ND2 port map( A => B(4), B => n1055, Z => n1084); U90 : ND2 port map( A => X_return86_11_port, B => n1053, Z => n1030); U91 : ND2 port map( A => B(5), B => n1055, Z => n1086); U92 : ND2 port map( A => X_return86_10_port, B => n1053, Z => n1032); U93 : ND2 port map( A => B(15), B => n1055, Z => n1088); U94 : ND2 port map( A => X_return86_0_port, B => n1053, Z => n1052); U95 : AO2 port map( A => n1089, B => n1090, C => n1056, D => A(6), Z => n1033); U96 : AO2 port map( A => n1089, B => n1091, C => n1059, D => A(7), Z => n1035); U97 : AO2 port map( A => n1089, B => n1092, C => n1061, D => A(8), Z => n1037); U98 : AO2 port map( A => n1089, B => n1093, C => n1063, D => A(9), Z => n1039); U99 : AO2 port map( A => n1089, B => n1094, C => n1065, D => A(10), Z => n1041); U100 : AO2 port map( A => n1089, B => n1095, C => n1067, D => A(11), Z => n1043); U101 : AO2 port map( A => n1089, B => n1096, C => n1069, D => A(12), Z => n1045); U102 : AO2 port map( A => n1089, B => n1097, C => n1071, D => A(13), Z => n1047); U103 : AO2 port map( A => n1089, B => n1098, C => n1073, D => A(14), Z => n1049); U104 : AO2 port map( A => n1089, B => n1099, C => n1075, D => A(0), Z => n599); U105 : AO2 port map( A => n1089, B => n1100, C => n1077, D => A(1), Z => n601); U106 : AO2 port map( A => n1089, B => n1101, C => n1079, D => A(2), Z => n1025); U107 : AO2 port map( A => n1089, B => n1102, C => n1081, D => A(3), Z => n1027); U108 : AO2 port map( A => n1089, B => n1103, C => n1083, D => A(4), Z => n1029); U109 : AO2 port map( A => n1089, B => n1104, C => n1085, D => A(5), Z => n1031); U110 : AO2 port map( A => n1089, B => n1105, C => n1087, D => A(15), Z => n1051); U111 : IV port map( A => A(6), Z => n1090); U112 : IV port map( A => A(7), Z => n1091); U113 : IV port map( A => A(8), Z => n1092); U114 : IV port map( A => A(9), Z => n1093); U115 : IV port map( A => A(10), Z => n1094); U116 : IV port map( A => A(11), Z => n1095); U117 : IV port map( A => A(12), Z => n1096); U118 : IV port map( A => A(13), Z => n1097); U119 : IV port map( A => A(14), Z => n1098); U120 : IV port map( A => A(0), Z => n1099); U121 : IV port map( A => A(1), Z => n1100); U122 : IV port map( A => A(2), Z => n1101); U123 : IV port map( A => A(3), Z => n1102); U124 : IV port map( A => A(4), Z => n1103); U125 : IV port map( A => A(5), Z => n1104); U126 : IV port map( A => A(15), Z => n1105); add_47_plus_plus : LC2_ALU_DW01_add_16_0 port map( A(0) => A(0), A(1) => A(1), A(2) => A(2), A(3) => A(3), A(4) => A(4), A(5) => A(5), A(6) => A(6), A(7) => A(7), A(8) => A(8), A(9) => A(9), A(10) => A(10), A(11) => A(11), A(12) => A(12), A(13) => A(13), A(14) => A(14), A(15) => A(15), B(0) => B(0), B(1) => B(1), B(2) => B(2), B(3) => B(3), B(4) => B(4), B(5) => B(5), B(6) => B(6), B(7) => B(7), B(8) => B(8), B(9) => B(9), B(10) => B(10), B(11) => B(11), B(12) => B(12), B(13) => B(13), B(14) => B(14), B(15) => B(15), CI => n1106, SUM(0) => X_return86_15_port, SUM(1) => X_return86_14_port, SUM(2) => X_return86_13_port, SUM(3) => X_return86_12_port, SUM(4) => X_return86_11_port, SUM(5) => X_return86_10_port, SUM(6) => X_return86_9_port, SUM(7) => X_return86_8_port, SUM(8) => X_return86_7_port, SUM(9) => X_return86_6_port, SUM(10) => X_return86_5_port, SUM(11) => X_return86_4_port, SUM(12) => X_return86_3_port, SUM(13) => X_return86_2_port, SUM(14) => X_return86_1_port, SUM(15) => X_return86_0_port, CO => open); n1106 <= '0'; end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity mem_logic is port( read_write : in std_logic; MAR : in std_logic_vector (0 to 15); MIO_enable : in std_logic; mem_enable : out std_logic; mux_sel_out : out std_logic_vector (0 to 1); KBSR_ld, CRTDR_ld, CRTSR_ld : out std_logic); end mem_logic; architecture SYN of mem_logic is component LD2 port( D, GN : in std_logic; Q, QN : out std_logic); end component; component AO7 port( A, B, C : in std_logic; Z : out std_logic); end component; component AN3 port( A, B, C : in std_logic; Z : out std_logic); end component; component AN4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component AO6 port( A, B, C : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component OR4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component ND4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component ND2 port( A, B : in std_logic; Z : out std_logic); end component; component OR3 port( A, B, C : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component NR4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component AO4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component EO1 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component EON1 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal n_540, n_539, n84, n85, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324 : std_logic; begin mux_sel_out_reg_1_label : LD2 port map( D => n_539, GN => n324, Q => mux_sel_out(0), QN => open); mux_sel_out_reg_0_label : LD2 port map( D => n_540, GN => n324, Q => mux_sel_out(1), QN => open); U42 : AO7 port map( A => MAR(15), B => n84, C => n85, Z => n_540); U43 : AO7 port map( A => n290, B => n291, C => n85, Z => n_539); U44 : AN3 port map( A => n292, B => n293, C => n294, Z => KBSR_ld); U45 : AN4 port map( A => n294, B => MAR(14), C => MAR(15), D => n295, Z => CRTDR_ld); U46 : AN3 port map( A => n296, B => n294, C => n295, Z => CRTSR_ld); U47 : AO6 port map( A => read_write, B => n292, C => n297, Z => n324); U48 : IV port map( A => MAR(3), Z => n298); U49 : IV port map( A => MAR(5), Z => n299); U50 : IV port map( A => MAR(8), Z => n300); U51 : IV port map( A => MAR(15), Z => n293); U52 : IV port map( A => MAR(10), Z => n301); U53 : IV port map( A => MAR(9), Z => n302); U54 : AN4 port map( A => MAR(0), B => MAR(1), C => n304, D => MAR(2), Z => n303); U55 : OR4 port map( A => n299, B => MAR(14), C => n305, D => n306, Z => n84) ; U56 : ND4 port map( A => n308, B => n303, C => n309, D => n310, Z => n307); U57 : IV port map( A => MAR(6), Z => n311); U58 : NR2 port map( A => MAR(15), B => MAR(14), Z => n296); U59 : ND4 port map( A => MAR(13), B => MAR(7), C => n312, D => n313, Z => n291); U60 : ND2 port map( A => MIO_enable, B => n303, Z => n314); U61 : NR2 port map( A => n314, B => n84, Z => n292); U62 : NR2 port map( A => n314, B => n291, Z => n295); U63 : IV port map( A => read_write, Z => n294); U64 : ND2 port map( A => MIO_enable, B => n307, Z => n315); U65 : NR2 port map( A => MAR(6), B => MAR(14), Z => n316); U66 : AO7 port map( A => MAR(14), B => n293, C => MAR(7), Z => n317); U67 : NR2 port map( A => MAR(7), B => MAR(6), Z => n318); U68 : ND4 port map( A => n300, B => n318, C => n302, D => n301, Z => n306); U69 : OR3 port map( A => MAR(13), B => MAR(11), C => MAR(12), Z => n305); U70 : NR2 port map( A => MAR(4), B => n298, Z => n304); U71 : AO2 port map( A => MAR(14), B => n293, C => MAR(8), D => n311, Z => n309); U72 : AN3 port map( A => n319, B => n320, C => n321, Z => n310); U73 : AN3 port map( A => MAR(11), B => n299, C => MAR(8), Z => n312); U74 : NR4 port map( A => n322, B => n301, C => n302, D => n311, Z => n313); U75 : ND2 port map( A => n295, B => n296, Z => n323); U76 : AO4 port map( A => n294, B => n315, C => n294, D => n323, Z => n297); U77 : IV port map( A => n315, Z => mem_enable); U78 : AO2 port map( A => MAR(11), B => MAR(5), C => n300, D => n299, Z => n320); U79 : EO1 port map( A => n317, B => MAR(13), C => n316, D => MAR(13), Z => n308); U80 : AO2 port map( A => MAR(7), B => n322, C => n302, D => MAR(12), Z => n319); U81 : EON1 port map( A => MAR(9), B => MAR(10), C => MAR(11), D => MAR(10), Z => n321); U82 : IV port map( A => n307, Z => n85); U83 : IV port map( A => n296, Z => n290); U84 : IV port map( A => MAR(12), Z => n322); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity sext is port( A : in std_logic_vector (0 to 4); O : out std_logic_vector (0 to 15) ); end sext; architecture SYN of sext is begin O <= ( A(0), A(0), A(0), A(0), A(0), A(0), A(0), A(0), A(0), A(0), A(0), A(0), A(1), A(2), A(3), A(4) ); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity NZP_logic is port( data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 2)); end NZP_logic; architecture SYN of NZP_logic is component LD1 port( D, G : in std_logic; Q, QN : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component NR4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component AN4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal n505, n506, n507, n508, n509, X_cell_1759_U1_CONTROL2, X_cell_1759_U1_CONTROL3 : std_logic; begin O_reg_2_label : LD1 port map( D => data(0), G => n505, Q => O(0), QN => open ); O_reg_1_label : LD1 port map( D => X_cell_1759_U1_CONTROL3, G => n505, Q => O(1), QN => open); O_reg_0_label : LD1 port map( D => X_cell_1759_U1_CONTROL2, G => n505, Q => O(2), QN => open); U103 : NR2 port map( A => data(0), B => X_cell_1759_U1_CONTROL3, Z => X_cell_1759_U1_CONTROL2); n505 <= '1'; U105 : NR4 port map( A => data(11), B => data(12), C => data(4), D => data(13), Z => n506); U106 : NR4 port map( A => data(5), B => data(10), C => data(0), D => data(8) , Z => n507); U107 : NR4 port map( A => data(15), B => data(6), C => data(3), D => data(14), Z => n508); U108 : NR4 port map( A => data(7), B => data(2), C => data(1), D => data(9), Z => n509); U109 : AN4 port map( A => n509, B => n508, C => n507, D => n506, Z => X_cell_1759_U1_CONTROL3); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity NZP_reg is port( clk, load : in std_logic; data : in std_logic_vector (0 to 2); O : out std_logic_vector (0 to 2); clear : in std_logic); end NZP_reg; architecture SYN of NZP_reg is component FJK2S port( J, K, CP, CD, TI, TE : in std_logic; Q, QN : out std_logic); end component; component FD1 port( D, CP : in std_logic; Q, QN : out std_logic); end component; component AO7 port( A, B, C : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component AN2 port( A, B : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal temp_2_port, O39_1_port, temp_0_port, O39_2_port, temp_1_port, O39_0_port, n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503, n504 : std_logic; begin temp_reg_2_label : FJK2S port map( J => n498, K => n498, CP => clk, CD => n500, TI => data(0), TE => load, Q => temp_2_port, QN => open); temp_reg_1_label : FJK2S port map( J => n499, K => n499, CP => clk, CD => n500, TI => data(1), TE => load, Q => temp_1_port, QN => open); temp_reg_0_label : FJK2S port map( J => n501, K => n501, CP => clk, CD => n500, TI => data(2), TE => load, Q => temp_0_port, QN => open); O_reg_2_label : FD1 port map( D => O39_2_port, CP => clk, Q => O(0), QN => n502); O_reg_1_label : FD1 port map( D => O39_1_port, CP => clk, Q => O(1), QN => n503); O_reg_0_label : FD1 port map( D => O39_0_port, CP => clk, Q => O(2), QN => n504); U25 : AO7 port map( A => n500, B => n502, C => n493, Z => O39_2_port); U26 : AO7 port map( A => n500, B => n503, C => n494, Z => O39_1_port); U27 : AO7 port map( A => n500, B => n504, C => n495, Z => O39_0_port); U28 : IV port map( A => clear, Z => n500); U29 : NR2 port map( A => clear, B => load, Z => n496); U30 : AN2 port map( A => load, B => n500, Z => n497); U31 : AO2 port map( A => temp_2_port, B => n496, C => data(0), D => n497, Z => n493); U32 : AO2 port map( A => temp_1_port, B => n496, C => data(1), D => n497, Z => n494); U33 : AO2 port map( A => temp_0_port, B => n496, C => data(2), D => n497, Z => n495); n498 <= '0'; n499 <= '0'; n501 <= '0'; end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity FSM is port( clk, rst : in std_logic; IR : in std_logic_vector (0 to 15); CC : in std_logic_vector (0 to 2); PC_ld : out std_logic; PC_mux : out std_logic_vector (0 to 1); IR_ld : out std_logic; MAR_mux : out std_logic_vector (0 to 1); MAR_gate : out std_logic; DR_addr : out std_logic_vector (0 to 2); DR_enable : out std_logic; SR1_addr, SR2_addr : out std_logic_vector (0 to 2); SR2_mux : out std_logic; ALU_sel : out std_logic_vector (0 to 1); CC_ld, MDR_ld, MAR_ld, PC_gate, ALU_gate, MDR_gate, MDR_mux, MIO_enable, Read_Write, PC_clear , MDR_clear, MAR_clear, IR_clear, CC_clear : out std_logic); end FSM; architecture SYN of FSM is component FJK2S port( J, K, CP, CD, TI, TE : in std_logic; Q, QN : out std_logic); end component; component FDS2L port( D, CP, CR, LD : in std_logic; Q, QN : out std_logic); end component; component AO7 port( A, B, C : in std_logic; Z : out std_logic); end component; component AO6 port( A, B, C : in std_logic; Z : out std_logic); end component; component AO4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component AO3 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component ND3 port( A, B, C : in std_logic; Z : out std_logic); end component; component ND2 port( A, B : in std_logic; Z : out std_logic); end component; component OR2 port( A, B : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component AO1 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component NR3 port( A, B, C : in std_logic; Z : out std_logic); end component; component AN3 port( A, B, C : in std_logic; Z : out std_logic); end component; component NR4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component OR3 port( A, B, C : in std_logic; Z : out std_logic); end component; component EON1 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component ND4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component AN2 port( A, B : in std_logic; Z : out std_logic); end component; component AN4 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component EO1 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal cpu_state_1_port, cpu_state_0_port, MAR_clear1208, execute_state954_2_port, TRAPVECTOR1338_2_port, DR1315_1_port, TRAPVECTOR_3_port, n1259, MAR_mux1365_1_port, TRAPVECTOR1338_6_port, n1289, SR1_addr1239_0_port, n1243_0_port, SR1_addr_0_port, DR_0_port, SR2_mux1349, TRAPVECTOR_7_port, cpu_state1017_0_port, DR_2_port, ALU_sel1354_1_port, PC_gate1218, SR1_addr_2_port, execute_state_1_port, TRAPVECTOR1338_4_port, SR1_addr1239_2_port, Read_Write1281, n1369_0_port, IR_ld1261, IR_clear1198, TRAPVECTOR_1_port, MDR_ld1266, n1279, TRAPVECTOR1338_0_port, PC_mux1291_1_port, ALU_gate1213, execute_state954_0_port, n1295_0_port, n1249_0_port, DR_enable1360, OPCODE1297_3_port, SR21309_1_port, DR_addr1233_2_port, OPCODE_2_port, MDR_clear1203, Imm, MAR_ld1256, SR2_addr1245_0_port, SR11303_0_port, link , n1363, OPCODE_0_port, n1216, n1231, n1211, n1264, SR11303_2_port, SR2_addr1245_2_port, DR_addr1233_0_port, OPCODE1297_1_port, SR21309_2_port, DR_addr1233_1_port, n1018_1_port, OPCODE1297_0_port, MDR_gate1228, PC_clear1193, n1226, PC_ld1276, n1274, OPCODE_3_port, OPCODE_1_port, SR2_addr1245_1_port, SR11303_1_port, n1254, n1221, n955_2_port, Imm1321, OPCODE1297_2_port, SR21309_0_port, n1284, DR1315_2_port, n1237_0_port, n1269, n1358_0_port, PC_mux1291_0_port, TRAPVECTOR1338_1_port, execute_state954_1_port, MDR_mux1286, CC_ld1271, TRAPVECTOR_4_port, MAR_gate1223, cpu_state1017_1_port, link1344, ALU_sel1354_0_port, n1347, execute_state_2_port, execute_state_0_port, MIO_enable_port, TRAPVECTOR1338_5_port, SR1_addr1239_1_port, TRAPVECTOR1338_7_port, SR1_addr_1_port, MIO_enable1251, DR_1_port, TRAPVECTOR_6_port, TRAPVECTOR1338_3_port, n1352, DR1315_0_port, MAR_mux1365_0_port, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210 : std_logic; begin SR1_addr <= ( SR1_addr_2_port, SR1_addr_1_port, SR1_addr_0_port ); MIO_enable <= MIO_enable_port; cpu_state_reg_1_label : FJK2S port map( J => n3121, K => n3121, CP => clk, CD => n3124, TI => cpu_state1017_1_port, TE => n1018_1_port, Q => cpu_state_1_port, QN => open); DR_addr_reg_2_label : FDS2L port map( D => DR_addr1233_2_port, CP => clk, CR => n3126, LD => n1237_0_port, Q => DR_addr(0), QN => n3127); DR_addr_reg_1_label : FDS2L port map( D => DR_addr1233_1_port, CP => clk, CR => n3128, LD => n1237_0_port, Q => DR_addr(1), QN => n3129); DR_addr_reg_0_label : FDS2L port map( D => DR_addr1233_0_port, CP => clk, CR => n3130, LD => n1237_0_port, Q => DR_addr(2), QN => n3131); SR1_addr_reg_2_label : FDS2L port map( D => SR1_addr1239_2_port, CP => clk, CR => n3132, LD => n1243_0_port, Q => SR1_addr_2_port, QN => open); SR1_addr_reg_1_label : FDS2L port map( D => SR1_addr1239_1_port, CP => clk, CR => n3133, LD => n1243_0_port, Q => SR1_addr_1_port, QN => open); SR1_addr_reg_0_label : FDS2L port map( D => SR1_addr1239_0_port, CP => clk, CR => n3134, LD => n1243_0_port, Q => SR1_addr_0_port, QN => open); SR2_addr_reg_2_label : FDS2L port map( D => SR2_addr1245_2_port, CP => clk, CR => n3135, LD => n1249_0_port, Q => SR2_addr(0), QN => n3136); SR2_addr_reg_1_label : FDS2L port map( D => SR2_addr1245_1_port, CP => clk, CR => n3137, LD => n1249_0_port, Q => SR2_addr(1), QN => n3138); SR2_addr_reg_0_label : FDS2L port map( D => SR2_addr1245_0_port, CP => clk, CR => n3139, LD => n1249_0_port, Q => SR2_addr(2), QN => n3140); PC_mux_reg_1_label : FDS2L port map( D => PC_mux1291_1_port, CP => clk, CR => n3141, LD => n1295_0_port, Q => PC_mux(0), QN => n3142); PC_mux_reg_0_label : FDS2L port map( D => PC_mux1291_0_port, CP => clk, CR => n3143, LD => n1295_0_port, Q => PC_mux(1), QN => n3144); DR_reg_2_label : FDS2L port map( D => DR1315_2_port, CP => clk, CR => n3155, LD => n1347, Q => DR_2_port, QN => open); DR_reg_1_label : FDS2L port map( D => DR1315_1_port, CP => clk, CR => n3156, LD => n1347, Q => DR_1_port, QN => open); DR_reg_0_label : FDS2L port map( D => DR1315_0_port, CP => clk, CR => n3157, LD => n1347, Q => DR_0_port, QN => open); TRAPVECTOR_reg_7_label : FDS2L port map( D => TRAPVECTOR1338_7_port, CP => clk, CR => n3158, LD => n1347, Q => TRAPVECTOR_7_port, QN => open); TRAPVECTOR_reg_6_label : FDS2L port map( D => TRAPVECTOR1338_6_port, CP => clk, CR => n3159, LD => n1347, Q => TRAPVECTOR_6_port, QN => open); TRAPVECTOR_reg_4_label : FDS2L port map( D => TRAPVECTOR1338_4_port, CP => clk, CR => n3161, LD => n1347, Q => TRAPVECTOR_4_port, QN => open); TRAPVECTOR_reg_3_label : FDS2L port map( D => TRAPVECTOR1338_3_port, CP => clk, CR => n3162, LD => n1347, Q => TRAPVECTOR_3_port, QN => open); TRAPVECTOR_reg_1_label : FDS2L port map( D => TRAPVECTOR1338_1_port, CP => clk, CR => n3164, LD => n1347, Q => TRAPVECTOR_1_port, QN => open); ALU_sel_reg_1_label : FDS2L port map( D => ALU_sel1354_1_port, CP => clk, CR => n3166, LD => n1358_0_port, Q => ALU_sel(0), QN => n3167); ALU_sel_reg_0_label : FDS2L port map( D => ALU_sel1354_0_port, CP => clk, CR => n3168, LD => n1358_0_port, Q => ALU_sel(1), QN => n3169); MAR_mux_reg_1_label : FDS2L port map( D => MAR_mux1365_1_port, CP => clk, CR => n3170, LD => n1369_0_port, Q => MAR_mux(0), QN => n3171); MAR_mux_reg_0_label : FDS2L port map( D => MAR_mux1365_0_port, CP => clk, CR => n3172, LD => n1369_0_port, Q => MAR_mux(1), QN => n3173); Imm_reg : FDS2L port map( D => Imm1321, CP => clk, CR => n3174, LD => n1347, Q => Imm, QN => open); MAR_ld_reg : FDS2L port map( D => MAR_ld1256, CP => clk, CR => n3175, LD => n1259, Q => MAR_ld, QN => n3176); PC_clear_reg : FDS2L port map( D => PC_clear1193, CP => clk, CR => n3177, LD => n1211, Q => PC_clear, QN => n3178); MDR_clear_reg : FDS2L port map( D => MDR_clear1203, CP => clk, CR => n3179, LD => n1211, Q => MDR_clear, QN => n3180); MDR_gate_reg : FDS2L port map( D => MDR_gate1228, CP => clk, CR => n3181, LD => n1231, Q => MDR_gate, QN => n3182); PC_gate_reg : FDS2L port map( D => PC_gate1218, CP => clk, CR => n3183, LD => n1221, Q => PC_gate, QN => n3184); Read_Write_reg : FDS2L port map( D => Read_Write1281, CP => clk, CR => n3185 , LD => n1284, Q => Read_Write, QN => n3186); IR_clear_reg : FDS2L port map( D => IR_clear1198, CP => clk, CR => n3187, LD => n1211, Q => IR_clear, QN => n3188); MDR_mux_reg : FDS2L port map( D => MDR_mux1286, CP => clk, CR => n3189, LD => n1289, Q => MDR_mux, QN => n3190); MAR_clear_reg : FDS2L port map( D => MAR_clear1208, CP => clk, CR => n3192, LD => n1211, Q => MAR_clear, QN => n3193); IR_ld_reg : FDS2L port map( D => IR_ld1261, CP => clk, CR => n3194, LD => n1264, Q => IR_ld, QN => n3195); MIO_enable_reg : FDS2L port map( D => MIO_enable1251, CP => clk, CR => n3196 , LD => n1254, Q => MIO_enable_port, QN => open); MAR_gate_reg : FDS2L port map( D => MAR_gate1223, CP => clk, CR => n3197, LD => n1226, Q => MAR_gate, QN => n3198); CC_ld_reg : FDS2L port map( D => CC_ld1271, CP => clk, CR => n3199, LD => n1274, Q => CC_ld, QN => n3200); DR_enable_reg : FDS2L port map( D => DR_enable1360, CP => clk, CR => n3201, LD => n1363, Q => DR_enable, QN => n3202); MDR_ld_reg : FDS2L port map( D => MDR_ld1266, CP => clk, CR => n3203, LD => n1269, Q => MDR_ld, QN => n3204); ALU_gate_reg : FDS2L port map( D => ALU_gate1213, CP => clk, CR => n3205, LD => n1216, Q => ALU_gate, QN => n3206); PC_ld_reg : FDS2L port map( D => PC_ld1276, CP => clk, CR => n3207, LD => n1279, Q => PC_ld, QN => n3208); SR2_mux_reg : FDS2L port map( D => SR2_mux1349, CP => clk, CR => n3209, LD => n1352, Q => SR2_mux, QN => n3210); OPCODE_reg_1_label : FDS2L port map( D => OPCODE1297_1_port, CP => clk, CR => n3147, LD => n1347, Q => OPCODE_1_port, QN => n2813); cpu_state_reg_0_label : FJK2S port map( J => n3120, K => n3120, CP => clk, CD => n3124, TI => cpu_state1017_0_port, TE => n1018_1_port, Q => cpu_state_0_port, QN => n2814); OPCODE_reg_3_label : FDS2L port map( D => OPCODE1297_3_port, CP => clk, CR => n3145, LD => n1347, Q => OPCODE_3_port, QN => n2815); execute_state_reg_2_label : FJK2S port map( J => n3125, K => n3125, CP => clk, CD => n3124, TI => execute_state954_2_port, TE => n955_2_port, Q => execute_state_2_port, QN => n2816); execute_state_reg_1_label : FJK2S port map( J => n3123, K => n3123, CP => clk, CD => n3124, TI => execute_state954_1_port, TE => n955_2_port, Q => execute_state_1_port, QN => n2817); OPCODE_reg_0_label : FDS2L port map( D => OPCODE1297_0_port, CP => clk, CR => n3148, LD => n1347, Q => OPCODE_0_port, QN => n2818); execute_state_reg_0_label : FJK2S port map( J => n3122, K => n3122, CP => clk, CD => n3124, TI => execute_state954_0_port, TE => n955_2_port, Q => execute_state_0_port, QN => n2819); OPCODE_reg_2_label : FDS2L port map( D => OPCODE1297_2_port, CP => clk, CR => n3146, LD => n1347, Q => OPCODE_2_port, QN => n2820); link_reg : FDS2L port map( D => link1344, CP => clk, CR => n3191, LD => n1347, Q => link, QN => n2821); TRAPVECTOR_reg_0_label : FDS2L port map( D => TRAPVECTOR1338_0_port, CP => clk, CR => n3165, LD => n1347, Q => open, QN => n2822); TRAPVECTOR_reg_2_label : FDS2L port map( D => TRAPVECTOR1338_2_port, CP => clk, CR => n3163, LD => n1347, Q => open, QN => n2823); TRAPVECTOR_reg_5_label : FDS2L port map( D => TRAPVECTOR1338_5_port, CP => clk, CR => n3160, LD => n1347, Q => open, QN => n2824); SR2_reg_2_label : FDS2L port map( D => SR21309_2_port, CP => clk, CR => n3152, LD => n1347, Q => open, QN => n2825); SR2_reg_0_label : FDS2L port map( D => SR21309_0_port, CP => clk, CR => n3154, LD => n1347, Q => open, QN => n2826); SR1_reg_2_label : FDS2L port map( D => SR11303_2_port, CP => clk, CR => n3149, LD => n1347, Q => open, QN => n2827); SR1_reg_1_label : FDS2L port map( D => SR11303_1_port, CP => clk, CR => n3150, LD => n1347, Q => open, QN => n2828); SR1_reg_0_label : FDS2L port map( D => SR11303_0_port, CP => clk, CR => n3151, LD => n1347, Q => open, QN => n2829); SR2_reg_1_label : FDS2L port map( D => SR21309_1_port, CP => clk, CR => n3153, LD => n1347, Q => open, QN => n2830); U1668 : AO7 port map( A => n3124, B => n3178, C => n2831, Z => PC_clear1193) ; U1669 : AO6 port map( A => n2833, B => n2834, C => rst, Z => n2832); U1670 : AO7 port map( A => n3124, B => n3188, C => n2831, Z => IR_clear1198) ; U1671 : AO7 port map( A => n3124, B => n3180, C => n2831, Z => MDR_clear1203 ); U1672 : AO7 port map( A => n3124, B => n3193, C => n2831, Z => MAR_clear1208 ); U1673 : AO4 port map( A => n3124, B => n3206, C => n2835, D => n2836, Z => ALU_gate1213); U1674 : AO7 port map( A => n2837, B => n2838, C => n2839, Z => n1216); U1675 : AO3 port map( A => n3124, B => n3184, C => n2840, D => n2841, Z => PC_gate1218); U1676 : ND3 port map( A => n3124, B => n2842, C => n2843, Z => n1221); U1677 : AO4 port map( A => n3124, B => n3198, C => n2844, D => n2836, Z => MAR_gate1223); U1678 : AO7 port map( A => n2845, B => n2838, C => n2839, Z => n1226); U1679 : AO3 port map( A => n3124, B => n3182, C => n2846, D => n2847, Z => MDR_gate1228); U1680 : AO3 port map( A => n2848, B => n2838, C => n2849, D => n2839, Z => n1231); U1681 : AO3 port map( A => n3124, B => n3127, C => n2850, D => n2851, Z => DR_addr1233_2_port); U1682 : AO3 port map( A => n3124, B => n3129, C => n2852, D => n2851, Z => DR_addr1233_1_port); U1683 : AO3 port map( A => n3124, B => n3131, C => n2853, D => n2851, Z => DR_addr1233_0_port); U1684 : AO7 port map( A => n2854, B => n2838, C => n2839, Z => n1237_0_port) ; U1685 : AO3 port map( A => n2855, B => n2827, C => n2856, D => n2857, Z => SR1_addr1239_2_port); U1686 : AO3 port map( A => n2855, B => n2828, C => n2856, D => n2858, Z => SR1_addr1239_1_port); U1687 : AO3 port map( A => n2855, B => n2829, C => n2856, D => n2859, Z => SR1_addr1239_0_port); U1688 : AO7 port map( A => n2860, B => n2838, C => n2839, Z => n1243_0_port) ; U1689 : AO4 port map( A => n3124, B => n3136, C => n2836, D => n2825, Z => SR2_addr1245_2_port); U1690 : AO4 port map( A => n3124, B => n3138, C => n2836, D => n2830, Z => SR2_addr1245_1_port); U1691 : AO4 port map( A => n3124, B => n3140, C => n2836, D => n2826, Z => SR2_addr1245_0_port); U1692 : AO7 port map( A => Imm, B => n2861, C => n2839, Z => n1249_0_port); U1693 : AO3 port map( A => execute_state_1_port, B => n2862, C => n2863, D => n2864, Z => MIO_enable1251); U1694 : AO3 port map( A => n2865, B => n2866, C => n2867, D => n2868, Z => n1254); U1695 : AO3 port map( A => n2869, B => n2838, C => n2842, D => n2868, Z => n1259); U1696 : AO4 port map( A => n3124, B => n3195, C => execute_state_2_port, D => n2836, Z => IR_ld1261); U1697 : ND2 port map( A => n2868, B => n2849, Z => n1264); U1698 : AO3 port map( A => n3124, B => n3204, C => n2870, D => n2841, Z => MDR_ld1266); U1699 : AO3 port map( A => n2871, B => n2838, C => n2872, D => n2868, Z => n1269); U1700 : AO4 port map( A => n3124, B => n3200, C => n2873, D => n2836, Z => CC_ld1271); U1701 : AO7 port map( A => n2874, B => n2838, C => n2868, Z => n1274); U1702 : AO3 port map( A => n3124, B => n3208, C => n2875, D => n2847, Z => PC_ld1276); U1703 : ND2 port map( A => n2876, B => n2877, Z => n1279); U1704 : ND2 port map( A => n2878, B => n2879, Z => n1284); U1705 : AO7 port map( A => n3124, B => n3190, C => n2880, Z => MDR_mux1286); U1706 : AO7 port map( A => n2881, B => n2838, C => n2878, Z => n1289); U1707 : AO4 port map( A => n3124, B => n3142, C => OPCODE_3_port, D => n2882 , Z => PC_mux1291_1_port); U1708 : AO7 port map( A => n3124, B => n3144, C => n2882, Z => PC_mux1291_0_port); U1709 : AO3 port map( A => n2883, B => n2866, C => n3124, D => n2884, Z => n1295_0_port); U1710 : AO7 port map( A => n2885, B => n2866, C => n3124, Z => n1347); U1711 : ND2 port map( A => n3124, B => n2861, Z => n1352); U1712 : AO7 port map( A => n2886, B => n2838, C => n3124, Z => n1358_0_port) ; U1713 : AO7 port map( A => n2887, B => n2838, C => n3124, Z => n1363); U1714 : AO7 port map( A => n2888, B => n2838, C => n3124, Z => n1369_0_port) ; U1715 : AO4 port map( A => n2889, B => n2838, C => cpu_state_0_port, D => n2890, Z => execute_state954_2_port); U1716 : AO4 port map( A => n2891, B => n2838, C => cpu_state_0_port, D => n2892, Z => execute_state954_1_port); U1717 : AO4 port map( A => execute_state_0_port, B => cpu_state_0_port, C => n2893, D => n2838, Z => execute_state954_0_port); U1718 : ND2 port map( A => n2894, B => cpu_state1017_0_port, Z => n955_2_port); U1719 : ND2 port map( A => cpu_state1017_0_port, B => n2866, Z => cpu_state1017_1_port); U1720 : OR2 port map( A => n2814, B => cpu_state_1_port, Z => cpu_state1017_0_port); U1721 : ND2 port map( A => n2895, B => cpu_state1017_0_port, Z => n1018_1_port); U1722 : IV port map( A => rst, Z => n3124); U1723 : ND2 port map( A => n2897, B => OPCODE_2_port, Z => n2896); U1724 : NR2 port map( A => n2899, B => n2900, Z => n2898); U1725 : AO1 port map( A => n2901, B => OPCODE_1_port, C => n2902, D => n2898 , Z => n2888); U1726 : AO1 port map( A => n2903, B => n2904, C => n2905, D => n2906, Z => n2887); U1727 : AO6 port map( A => n2907, B => n2908, C => n2909, Z => n2886); U1728 : NR3 port map( A => n2911, B => OPCODE_3_port, C => n2899, Z => n2910 ); U1729 : AO1 port map( A => n2912, B => n2913, C => n2914, D => n2915, Z => n2881); U1730 : NR2 port map( A => n2911, B => n2917, Z => n2916); U1731 : AO1 port map( A => n2919, B => n2920, C => n2921, D => n2922, Z => n2918); U1732 : AO1 port map( A => n2904, B => n2923, C => n2906, D => n2918, Z => n2874); U1733 : AO1 port map( A => n2924, B => n2904, C => n2925, D => n2926, Z => n2871); U1734 : AO6 port map( A => n2920, B => n2928, C => n2929, Z => n2927); U1735 : AO1 port map( A => n2930, B => n2833, C => n2931, D => n2927, Z => n2869); U1736 : AO6 port map( A => n2932, B => n2933, C => n2909, Z => n2860); U1737 : AN3 port map( A => link, B => n2818, C => n2935, Z => n2934); U1738 : NR2 port map( A => n2934, B => n2937, Z => n2936); U1739 : NR2 port map( A => n2903, B => n2939, Z => n2938); U1740 : AO1 port map( A => n2940, B => n2913, C => n2941, D => n2942, Z => n2854); U1741 : AO7 port map( A => n2939, B => n2944, C => n2904, Z => n2943); U1742 : NR2 port map( A => n2890, B => n2946, Z => n2945); U1743 : AO1 port map( A => n2947, B => n2948, C => n2949, D => n2945, Z => n2848); U1744 : AO1 port map( A => n2950, B => n2833, C => n2951, D => n2931, Z => n2845); U1745 : AO3 port map( A => n2921, B => n2953, C => n2954, D => n2955, Z => n2952); U1746 : NR2 port map( A => n2957, B => n2947, Z => n2956); U1747 : AO1 port map( A => n2958, B => n2959, C => n2960, D => n2961, Z => n2889); U1748 : AO6 port map( A => execute_state_0_port, B => execute_state_2_port, C => n2963, Z => n2962); U1749 : AO1 port map( A => n2958, B => n2964, C => n2965, D => n2966, Z => n2891); U1750 : NR4 port map( A => n2967, B => n2968, C => n2966, D => n2961, Z => n2893); U1751 : ND2 port map( A => execute_state_1_port, B => OPCODE_0_port, Z => n2969); U1752 : AN3 port map( A => cpu_state_0_port, B => n2971, C => n2972, Z => n2970); U1753 : AO1 port map( A => link, B => n2818, C => n2974, D => OPCODE_1_port, Z => n2973); U1754 : NR2 port map( A => n2907, B => n2976, Z => n2975); U1755 : AO1 port map( A => n2976, B => execute_state_2_port, C => OPCODE_2_port, D => n2978, Z => n2977); U1756 : NR2 port map( A => OPCODE_2_port, B => n2816, Z => n2979); U1757 : NR2 port map( A => n2981, B => n2813, Z => n2980); U1758 : AO2 port map( A => n2983, B => n2819, C => cpu_state_0_port, D => n2984, Z => n2982); U1759 : AO6 port map( A => link, B => n2813, C => n2820, Z => n2985); U1760 : NR2 port map( A => execute_state_0_port, B => n2985, Z => n2986); U1761 : AO1 port map( A => n2813, B => n2817, C => n2987, D => n2986, Z => n2844); U1762 : NR2 port map( A => n2989, B => n2990, Z => n2988); U1763 : AN3 port map( A => n2818, B => n2819, C => n2815, Z => n2991); U1764 : AO1 port map( A => n2820, B => n2816, C => n2993, D => n2991, Z => n2992); U1765 : AO1 port map( A => n2993, B => n2818, C => n2995, D => n2996, Z => n2994); U1766 : NR2 port map( A => n2813, B => n2818, Z => n2997); U1767 : AO1 port map( A => n2813, B => n2816, C => n2998, D => n2993, Z => n2873); U1768 : AO6 port map( A => OPCODE_1_port, B => n2974, C => n3000, Z => n2999 ); U1769 : NR2 port map( A => execute_state_0_port, B => n2815, Z => n3001); U1770 : AO1 port map( A => OPCODE_2_port, B => n2816, C => n3003, D => n3001 , Z => n3002); U1771 : NR2 port map( A => n2993, B => n3004, Z => n2835); U1772 : NR2 port map( A => n2815, B => OPCODE_2_port, Z => n3005); U1773 : NR2 port map( A => n3006, B => n2813, Z => n2990); U1774 : NR2 port map( A => n2815, B => n2907, Z => n3007); U1775 : NR2 port map( A => n2817, B => n2816, Z => n3008); U1776 : NR2 port map( A => n2820, B => n2815, Z => n2935); U1777 : NR2 port map( A => OPCODE_0_port, B => OPCODE_1_port, Z => n3009); U1778 : OR3 port map( A => execute_state_2_port, B => n2974, C => n2899, Z => n3010); U1779 : NR2 port map( A => n2817, B => execute_state_0_port, Z => n3011); U1780 : NR2 port map( A => execute_state_2_port, B => execute_state_1_port, Z => n2833); U1781 : NR2 port map( A => n2917, B => n2819, Z => n3012); U1782 : ND3 port map( A => n2821, B => n2935, C => n3012, Z => n2900); U1783 : ND2 port map( A => cpu_state_1_port, B => cpu_state_0_port, Z => n2838); U1784 : NR2 port map( A => n2820, B => OPCODE_3_port, Z => n2981); U1785 : ND2 port map( A => n2981, B => n3009, Z => n3013); U1786 : NR2 port map( A => n2974, B => n2818, Z => n3014); U1787 : OR2 port map( A => n2968, B => n2957, Z => n3015); U1788 : NR2 port map( A => n3015, B => execute_state_2_port, Z => n3016); U1789 : NR3 port map( A => OPCODE_0_port, B => n2813, C => n2974, Z => n2937 ); U1790 : NR2 port map( A => n2929, B => OPCODE_0_port, Z => n2913); U1791 : ND2 port map( A => n2981, B => OPCODE_1_port, Z => n3017); U1792 : NR2 port map( A => n2816, B => execute_state_1_port, Z => n2947); U1793 : ND2 port map( A => n2989, B => n2818, Z => n3018); U1794 : NR2 port map( A => OPCODE_3_port, B => OPCODE_2_port, Z => n3019); U1795 : NR2 port map( A => n2922, B => n2813, Z => n2930); U1796 : NR3 port map( A => n3020, B => n2963, C => n3008, Z => n2904); U1797 : NR2 port map( A => n3021, B => OPCODE_0_port, Z => n2939); U1798 : NR2 port map( A => n2818, B => OPCODE_1_port, Z => n2907); U1799 : NR2 port map( A => n2921, B => n2935, Z => n2903); U1800 : ND2 port map( A => n3022, B => n3023, Z => n2906); U1801 : AO3 port map( A => n3024, B => n2917, C => n3025, D => n3026, Z => n2905); U1802 : NR2 port map( A => n2818, B => OPCODE_3_port, Z => n2978); U1803 : NR2 port map( A => n2917, B => execute_state_0_port, Z => n2932); U1804 : NR2 port map( A => execute_state_2_port, B => execute_state_0_port, Z => n3020); U1805 : NR2 port map( A => n3017, B => n2818, Z => n3027); U1806 : NR2 port map( A => n2819, B => n2817, Z => n2957); U1807 : ND2 port map( A => n2957, B => n2816, Z => n2883); U1808 : NR2 port map( A => n2818, B => n2929, Z => n2944); U1809 : AO7 port map( A => n2883, B => n3028, C => n3029, Z => n2909); U1810 : NR2 port map( A => n3030, B => n2819, Z => n2912); U1811 : ND2 port map( A => cpu_state_1_port, B => n2814, Z => n2866); U1812 : ND2 port map( A => n2947, B => n2819, Z => n2920); U1813 : ND2 port map( A => n3014, B => OPCODE_1_port, Z => n3031); U1814 : NR2 port map( A => n2921, B => n2974, Z => n3032); U1815 : NR3 port map( A => n2976, B => n2813, C => n2820, Z => n2924); U1816 : NR2 port map( A => n3034, B => execute_state_2_port, Z => n3033); U1817 : AO6 port map( A => n3012, B => n2983, C => rst, Z => n2878); U1818 : OR3 port map( A => OPCODE_0_port, B => OPCODE_2_port, C => n2813, Z => n3035); U1819 : ND2 port map( A => n3018, B => n3031, Z => n2948); U1820 : NR2 port map( A => n2819, B => execute_state_1_port, Z => n2963); U1821 : NR2 port map( A => cpu_state_0_port, B => cpu_state_1_port, Z => n2834); U1822 : AO6 port map( A => n3033, B => n2834, C => rst, Z => n2868); U1823 : ND2 port map( A => execute_state_1_port, B => n2816, Z => n3036); U1824 : NR2 port map( A => n3021, B => n2818, Z => n3037); U1825 : EON1 port map( A => n3030, B => n3028, C => n3016, D => n3037, Z => n2926); U1826 : ND4 port map( A => n2932, B => n2907, C => n3038, D => n2815, Z => n2861); U1827 : AO6 port map( A => n2932, B => n2834, C => rst, Z => n2839); U1828 : NR2 port map( A => n3034, B => n2816, Z => n2940); U1829 : AN2 port map( A => n3039, B => n3040, Z => n2911); U1830 : ND2 port map( A => n3042, B => n3043, Z => n3041); U1831 : NR2 port map( A => n2819, B => n3045, Z => n3044); U1832 : NR2 port map( A => n2815, B => OPCODE_0_port, Z => n2976); U1833 : AN2 port map( A => n2883, B => n3047, Z => n3046); U1834 : NR2 port map( A => n2897, B => OPCODE_2_port, Z => n2958); U1835 : NR2 port map( A => n2948, B => n3037, Z => n3048); U1836 : ND2 port map( A => cpu_state_1_port, B => n3124, Z => n2836); U1837 : NR2 port map( A => n2820, B => execute_state_1_port, Z => n2987); U1838 : AO7 port map( A => n3049, B => n3050, C => n3051, Z => n2855); U1839 : AO1 port map( A => n2969, B => OPCODE_2_port, C => n2813, D => n2836 , Z => n3052); U1840 : NR2 port map( A => n2814, B => rst, Z => n3053); U1841 : NR2 port map( A => n2836, B => cpu_state_0_port, Z => n3054); U1842 : NR2 port map( A => n2974, B => execute_state_1_port, Z => n2993); U1843 : AO4 port map( A => execute_state_2_port, B => n2922, C => execute_state_0_port, D => n2988, Z => n2998); U1844 : AO3 port map( A => n3044, B => n2929, C => n3056, D => n2946, Z => n3055); U1845 : AO3 port map( A => n3028, B => n3047, C => n3058, D => n3059, Z => n3057); U1846 : EON1 port map( A => n2821, B => n3124, C => IR(4), D => n3124, Z => link1344); U1847 : EON1 port map( A => n3060, B => rst, C => TRAPVECTOR_7_port, D => rst, Z => TRAPVECTOR1338_7_port); U1848 : EON1 port map( A => n3061, B => rst, C => TRAPVECTOR_6_port, D => rst, Z => TRAPVECTOR1338_6_port); U1849 : EON1 port map( A => n2824, B => n3124, C => IR(10), D => n3124, Z => TRAPVECTOR1338_5_port); U1850 : AO2 port map( A => TRAPVECTOR_4_port, B => rst, C => IR(11), D => n3124, Z => n3062); U1851 : AO2 port map( A => TRAPVECTOR_3_port, B => rst, C => IR(12), D => n3124, Z => n3063); U1852 : AO2 port map( A => n3064, B => n3124, C => n2823, D => rst, Z => TRAPVECTOR1338_2_port); U1853 : EON1 port map( A => n3065, B => rst, C => TRAPVECTOR_1_port, D => rst, Z => TRAPVECTOR1338_1_port); U1854 : AO2 port map( A => n3066, B => n3124, C => n2822, D => rst, Z => TRAPVECTOR1338_0_port); U1855 : AO2 port map( A => Imm, B => n3124, C => n3210, D => rst, Z => SR2_mux1349); U1856 : AO2 port map( A => n3064, B => n3124, C => n2825, D => rst, Z => SR21309_2_port); U1857 : AO4 port map( A => n2830, B => n3124, C => n3065, D => rst, Z => SR21309_1_port); U1858 : AO2 port map( A => n3066, B => n3124, C => n2826, D => rst, Z => SR21309_0_port); U1859 : EON1 port map( A => n2827, B => n3124, C => IR(7), D => n3124, Z => SR11303_2_port); U1860 : AO4 port map( A => n2828, B => n3124, C => n3060, D => rst, Z => SR11303_1_port); U1861 : AO4 port map( A => n2829, B => n3124, C => n3061, D => rst, Z => SR11303_0_port); U1862 : NR2 port map( A => execute_state_2_port, B => n2815, Z => n3067); U1863 : AO2 port map( A => n2970, B => n3124, C => n3186, D => rst, Z => Read_Write1281); U1864 : EON1 port map( A => n2815, B => n3124, C => IR(0), D => n3124, Z => OPCODE1297_3_port); U1865 : EON1 port map( A => n2820, B => n3124, C => IR(1), D => n3124, Z => OPCODE1297_2_port); U1866 : EON1 port map( A => n2813, B => n3124, C => IR(2), D => n3124, Z => OPCODE1297_1_port); U1867 : EON1 port map( A => n2818, B => n3124, C => IR(3), D => n3124, Z => OPCODE1297_0_port); U1868 : AO2 port map( A => n3069, B => n2818, C => n3070, D => OPCODE_0_port , Z => n3068); U1869 : AO2 port map( A => n2977, B => n2819, C => n3072, D => execute_state_0_port, Z => n3071); U1870 : NR2 port map( A => execute_state_0_port, B => n2922, Z => n3073); U1871 : AO7 port map( A => OPCODE_2_port, B => n2920, C => n3069, Z => n3074 ); U1872 : NR2 port map( A => execute_state_2_port, B => n2976, Z => n3075); U1873 : AO2 port map( A => n2971, B => n3124, C => n3171, D => rst, Z => MAR_mux1365_1_port); U1874 : AO2 port map( A => n2980, B => n3124, C => n3173, D => rst, Z => MAR_mux1365_0_port); U1875 : AO2 port map( A => n2982, B => n3124, C => n3176, D => rst, Z => MAR_ld1256); U1876 : AO2 port map( A => Imm, B => rst, C => IR(10), D => n3124, Z => n3076); U1877 : AO2 port map( A => n2994, B => n3124, C => n3202, D => rst, Z => DR_enable1360); U1878 : AO2 port map( A => DR_2_port, B => rst, C => IR(4), D => n3124, Z => n3077); U1879 : AO2 port map( A => DR_1_port, B => rst, C => IR(5), D => n3124, Z => n3078); U1880 : AO2 port map( A => DR_0_port, B => rst, C => IR(6), D => n3124, Z => n3079); U1881 : AO2 port map( A => n2999, B => n3124, C => n3167, D => rst, Z => ALU_sel1354_1_port); U1882 : AO2 port map( A => n3080, B => n3124, C => n3169, D => rst, Z => ALU_sel1354_0_port); U1883 : AO2 port map( A => n3081, B => n2813, C => n3002, D => OPCODE_1_port , Z => n3004); U1884 : AO2 port map( A => n2937, B => n3016, C => n2913, D => n3008, Z => n3023); U1885 : AO2 port map( A => n2939, B => n2904, C => n3082, D => n2947, Z => n3022); U1886 : AO2 port map( A => n2932, B => n2978, C => n3027, D => n3020, Z => n3029); U1887 : AO2 port map( A => IR(6), B => CC(2), C => IR(4), D => CC(0), Z => n3039); U1888 : AO3 port map( A => OPCODE_1_port, B => n2900, C => n3084, D => n3026 , Z => n3083); U1889 : EON1 port map( A => n2920, B => n3031, C => n3012, D => n3032, Z => n3085); U1890 : AO4 port map( A => n2883, B => n3086, C => n2919, D => n3021, Z => n2915); U1891 : AO4 port map( A => n3028, B => n2920, C => n2929, D => n3087, Z => n2914); U1892 : AO4 port map( A => n3048, B => n3087, C => n2919, D => n3035, Z => n3088); U1893 : AO4 port map( A => n3028, B => n3090, C => n3091, D => n2920, Z => n3089); U1894 : AO3 port map( A => n3093, B => n3010, C => n3094, D => n2955, Z => n3092); U1895 : AO4 port map( A => n3030, B => n3031, C => n2917, D => n3013, Z => n3095); U1896 : AO3 port map( A => n3035, B => n3036, C => n3096, D => n3097, Z => n2925); U1897 : AO4 port map( A => n2865, B => n3035, C => n3048, D => n3036, Z => n3098); U1898 : AO4 port map( A => n3015, B => n3028, C => n3091, D => n3030, Z => n3099); U1899 : AO4 port map( A => n2936, B => n2919, C => n2938, D => n2883, Z => n2942); U1900 : AO4 port map( A => n3024, B => n3100, C => n3018, D => n2920, Z => n2941); U1901 : NR2 port map( A => OPCODE_2_port, B => n2813, Z => n2950); U1902 : EON1 port map( A => n3093, B => n3010, C => n2937, D => n3020, Z => n2951); U1903 : AO2 port map( A => n2905, B => n3038, C => n2814, D => n2932, Z => n2843); U1904 : AO4 port map( A => n3087, B => n3006, C => n2920, D => n2935, Z => n3101); U1905 : AO6 port map( A => n2904, B => n3027, C => n2926, Z => n2954); U1906 : NR4 port map( A => TRAPVECTOR_7_port, B => TRAPVECTOR_6_port, C => TRAPVECTOR_4_port, D => TRAPVECTOR_3_port, Z => n3043); U1907 : NR4 port map( A => TRAPVECTOR_1_port, B => n2822, C => n2823, D => n2824, Z => n3042); U1908 : AO2 port map( A => n2912, B => n3102, C => n3044, D => n2913, Z => n3059); U1909 : NR2 port map( A => n2939, B => n2937, Z => n3103); U1910 : AO4 port map( A => n2890, B => n3104, C => n2956, D => n3028, Z => n2960); U1911 : AO4 port map( A => n3104, B => n2892, C => n2962, D => n3028, Z => n2965); U1912 : EON1 port map( A => execute_state_0_port, B => n3104, C => n3011, D => n2958, Z => n2967); U1913 : OR2 port map( A => n2903, B => n3082, Z => n3049); U1914 : AO4 port map( A => n2974, B => n2899, C => n2818, D => n3105, Z => n3050); U1915 : AO2 port map( A => DR_2_port, B => n3052, C => SR1_addr_2_port, D => rst, Z => n2857); U1916 : AO2 port map( A => DR_1_port, B => n3052, C => SR1_addr_1_port, D => rst, Z => n2858); U1917 : AO2 port map( A => DR_0_port, B => n3052, C => SR1_addr_0_port, D => rst, Z => n2859); U1918 : AO2 port map( A => n2976, B => n2912, C => n3033, D => OPCODE_3_port , Z => n3106); U1919 : EON1 port map( A => OPCODE_1_port, B => n2992, C => n2816, D => n2978, Z => n2996); U1920 : AO6 port map( A => n2819, B => n3014, C => n2998, Z => n3107); U1921 : IV port map( A => n3011, Z => n3034); U1922 : IV port map( A => IR(13), Z => n3064); U1923 : IV port map( A => IR(15), Z => n3066); U1924 : IV port map( A => n2944, Z => n3028); U1925 : IV port map( A => n2833, Z => n2917); U1926 : IV port map( A => n2836, Z => n3051); U1927 : IV port map( A => n2990, Z => n2929); U1928 : IV port map( A => n2947, Z => n3030); U1929 : IV port map( A => n2838, Z => n3038); U1930 : IV port map( A => n2907, Z => n2921); U1931 : IV port map( A => n3053, Z => n2882); U1932 : IV port map( A => n3012, Z => n2919); U1933 : IV port map( A => n2932, Z => n3100); U1934 : IV port map( A => n3019, Z => n2922); U1935 : IV port map( A => n3014, Z => n2971); U1936 : NR2 port map( A => n3087, B => n3028, Z => n2966); U1937 : IV port map( A => n2966, Z => n3097); U1938 : NR3 port map( A => n3034, B => n3010, C => n2821, Z => n2902); U1939 : IV port map( A => n2902, Z => n3026); U1940 : NR2 port map( A => n3086, B => n2865, Z => n2931); U1941 : ND2 port map( A => n3124, B => n2819, Z => n2831); U1942 : IV port map( A => n2963, Z => n3090); U1943 : NR2 port map( A => execute_state_1_port, B => execute_state_0_port, Z => n2968); U1944 : ND2 port map( A => n3054, B => n2819, Z => n2841); U1945 : ND2 port map( A => n2983, B => n2833, Z => n2842); U1946 : ND2 port map( A => n3054, B => n2816, Z => n2847); U1947 : ND2 port map( A => n2983, B => n2904, Z => n2849); U1948 : AO7 port map( A => n2997, B => n3009, C => n3051, Z => n2851); U1949 : NR3 port map( A => n2816, B => n3031, C => n3041, Z => n2961); U1950 : ND2 port map( A => n3032, B => n3016, Z => n2955); U1951 : ND2 port map( A => n3051, B => n3014, Z => n2856); U1952 : IV port map( A => n3009, Z => n2899); U1953 : IV port map( A => n2866, Z => n2983); U1954 : IV port map( A => n2913, Z => n2946); U1955 : IV port map( A => n3005, Z => n3006); U1956 : IV port map( A => n3033, Z => n3087); U1957 : IV port map( A => n3016, Z => n2865); U1958 : IV port map( A => n2924, Z => n3086); U1959 : IV port map( A => n2930, Z => n3021); U1960 : IV port map( A => n2987, Z => n3105); U1961 : NR2 port map( A => n2922, B => execute_state_1_port, Z => n3003); U1962 : IV port map( A => n3003, Z => n3069); U1963 : IV port map( A => n2940, Z => n3047); U1964 : IV port map( A => n3054, Z => n2862); U1965 : IV port map( A => n3008, Z => n3045); U1966 : AO7 port map( A => OPCODE_2_port, B => n3108, C => n3045, Z => n3056 ); U1967 : IV port map( A => n2935, Z => n2974); U1968 : IV port map( A => n2976, Z => n2897); U1969 : AO6 port map( A => link, B => n3109, C => n3110, Z => n3024); U1970 : ND4 port map( A => n3012, B => link, C => n3009, D => OPCODE_2_port, Z => n3025); U1971 : AO4 port map( A => n2820, B => n3100, C => n3006, D => n2919, Z => n2908); U1972 : ND2 port map( A => IR(5), B => CC(1), Z => n3040); U1973 : AO7 port map( A => n2910, B => n3109, C => n2932, Z => n3084); U1974 : AO7 port map( A => n3083, B => n3085, C => n3038, Z => n2884); U1975 : NR2 port map( A => n3027, B => n2913, Z => n3091); U1976 : AO7 port map( A => n3088, B => n3089, C => n3038, Z => n2879); U1977 : IV port map( A => n1264, Z => n2877); U1978 : AO6 port map( A => n2821, B => execute_state_0_port, C => execute_state_1_port, Z => n3093); U1979 : AO3 port map( A => n2916, B => n3012, C => n3009, D => n3019, Z => n3094); U1980 : AO7 port map( A => n3092, B => n3095, C => n3038, Z => n2876); U1981 : EON1 port map( A => n3006, B => n2921, C => n2981, D => n2907, Z => n2923); U1982 : OR3 port map( A => n3015, B => n2816, C => n2946, Z => n3096); U1983 : OR2 port map( A => n3036, B => n2866, Z => n2872); U1984 : ND2 port map( A => n3034, B => n2816, Z => n2928); U1985 : AO7 port map( A => n3098, B => n3099, C => n3038, Z => n2867); U1986 : AO3 port map( A => OPCODE_1_port, B => n2974, C => n3017, D => n2921 , Z => n2933); U1987 : AO6 port map( A => n2819, B => execute_state_2_port, C => n2957, Z => n2890); U1988 : AO6 port map( A => n2815, B => n3012, C => n3101, Z => n2953); U1989 : AO7 port map( A => n2818, B => n3041, C => OPCODE_2_port, Z => n3111 ); U1990 : ND2 port map( A => n3007, B => n3111, Z => n3102); U1991 : ND4 port map( A => n2911, B => n2932, C => n3019, D => n3009, Z => n3058); U1992 : AN4 port map( A => n3048, B => OPCODE_1_port, C => n3103, D => n3112 , Z => n3104); U1993 : ND2 port map( A => n3046, B => n3030, Z => n2959); U1994 : NR2 port map( A => n3011, B => n3012, Z => n2892); U1995 : ND2 port map( A => n3034, B => n3090, Z => n2964); U1996 : AO4 port map( A => execute_state_0_port, B => n2973, C => execute_state_1_port, D => n2975, Z => n3113); U1997 : ND2 port map( A => n3053, B => n3113, Z => n2875); U1998 : NR2 port map( A => n2815, B => OPCODE_1_port, Z => n3000); U1999 : ND2 port map( A => n3114, B => n3053, Z => n2840); U2000 : AO7 port map( A => n3068, B => n3071, C => n3053, Z => n2863); U2001 : ND2 port map( A => MIO_enable_port, B => rst, Z => n2864); U2002 : AO3 port map( A => n2979, B => n2815, C => OPCODE_0_port, D => n3053 , Z => n2880); U2003 : AO3 port map( A => execute_state_2_port, B => n2820, C => n3116, D => n3106, Z => n3115); U2004 : ND2 port map( A => n3053, B => n3115, Z => n2870); U2005 : AO7 port map( A => n3046, B => n2897, C => n3118, Z => n3117); U2006 : ND2 port map( A => n3053, B => n3117, Z => n2846); U2007 : AO3 port map( A => n3005, B => n2976, C => n3015, D => n2816, Z => n3119); U2008 : AO3 port map( A => execute_state_0_port, B => n2922, C => n3119, D => n3105, Z => n2984); U2009 : ND2 port map( A => DR_2_port, B => n3051, Z => n2850); U2010 : ND2 port map( A => DR_1_port, B => n3051, Z => n2852); U2011 : ND2 port map( A => DR_0_port, B => n3051, Z => n2853); U2012 : AO2 port map( A => n3045, B => n2814, C => n3055, D => cpu_state_0_port, Z => n2894); U2013 : EO1 port map( A => n3100, B => n2896, C => n3012, D => n2896, Z => n2901); U2014 : AO2 port map( A => n2912, B => n2814, C => n3057, D => cpu_state_0_port, Z => n2895); U2015 : AO2 port map( A => n2974, B => n2818, C => n3067, D => OPCODE_0_port , Z => n2972); U2016 : EO1 port map( A => execute_state_1_port, B => n3000, C => n2819, D => n3000, Z => n3114); U2017 : ND2 port map( A => n3005, B => n2817, Z => n3070); U2018 : ND2 port map( A => n2976, B => n2816, Z => n3072); U2019 : AO2 port map( A => n3073, B => n2818, C => n3074, D => OPCODE_0_port , Z => n3116); U2020 : AO2 port map( A => n3075, B => n2820, C => n2819, D => OPCODE_2_port , Z => n3118); U2021 : AO7 port map( A => n2981, B => n3005, C => n2813, Z => n3080); U2022 : ND2 port map( A => n2974, B => n2816, Z => n3081); U2023 : IV port map( A => n2943, Z => n2949); U2024 : IV port map( A => n2952, Z => n2837); U2025 : IV port map( A => n3027, Z => n3112); U2026 : IV port map( A => n3017, Z => n2989); U2027 : IV port map( A => n3062, Z => TRAPVECTOR1338_4_port); U2028 : IV port map( A => n3063, Z => TRAPVECTOR1338_3_port); U2029 : IV port map( A => n3078, Z => DR1315_1_port); U2030 : IV port map( A => n3079, Z => DR1315_0_port); U2031 : IV port map( A => n3018, Z => n3082); U2032 : IV port map( A => IR(14), Z => n3065); U2033 : IV port map( A => IR(8), Z => n3060); U2034 : IV port map( A => IR(9), Z => n3061); U2035 : IV port map( A => n3013, Z => n3109); U2036 : IV port map( A => n3076, Z => Imm1321); U2037 : IV port map( A => n3077, Z => DR1315_2_port); U2038 : IV port map( A => n3007, Z => n3108); U2039 : IV port map( A => n3031, Z => n3110); U2040 : IV port map( A => n2912, Z => n2885); U2041 : IV port map( A => n2832, Z => n1211); U2042 : IV port map( A => n3107, Z => n2995); n3120 <= '0'; n3121 <= '0'; n3122 <= '0'; n3123 <= '0'; n3125 <= '0'; n3126 <= '1'; n3128 <= '1'; n3130 <= '1'; n3132 <= '1'; n3133 <= '1'; n3134 <= '1'; n3135 <= '1'; n3137 <= '1'; n3139 <= '1'; n3141 <= '1'; n3143 <= '1'; n3145 <= '1'; n3146 <= '1'; n3147 <= '1'; n3148 <= '1'; n3149 <= '1'; n3150 <= '1'; n3151 <= '1'; n3152 <= '1'; n3153 <= '1'; n3154 <= '1'; n3155 <= '1'; n3156 <= '1'; n3157 <= '1'; n3158 <= '1'; n3159 <= '1'; n3160 <= '1'; n3161 <= '1'; n3162 <= '1'; n3163 <= '1'; n3164 <= '1'; n3165 <= '1'; n3166 <= '1'; n3168 <= '1'; n3170 <= '1'; n3172 <= '1'; n3174 <= '1'; n3175 <= '1'; n3177 <= '1'; n3179 <= '1'; n3181 <= '1'; n3183 <= '1'; n3185 <= '1'; n3187 <= '1'; n3189 <= '1'; n3191 <= '1'; n3192 <= '1'; n3194 <= '1'; n3196 <= '1'; n3197 <= '1'; n3199 <= '1'; n3201 <= '1'; n3203 <= '1'; n3205 <= '1'; n3207 <= '1'; n3209 <= '1'; CC_clear <= '0'; end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity zext8 is port( A : in std_logic_vector (0 to 7); O : out std_logic_vector (0 to 15) ); end zext8; architecture SYN of zext8 is signal O_8_port : std_logic; begin O <= ( O_8_port, O_8_port, O_8_port, O_8_port, O_8_port, O_8_port, O_8_port, O_8_port, A(0), A(1), A(2), A(3), A(4), A(5), A(6), A(7) ); O_8_port <= '0'; end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity zext10 is port( A : in std_logic_vector (0 to 5); O : out std_logic_vector (0 to 15) ); end zext10; architecture SYN of zext10 is signal O_6_port : std_logic; begin O <= ( O_6_port, O_6_port, O_6_port, O_6_port, O_6_port, O_6_port, O_6_port, O_6_port, O_6_port, O_6_port, A(0), A(1), A(2), A(3), A(4), A(5) ); O_6_port <= '0'; end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity adder_DW01_add_16_0 is port( A, B : in std_logic_vector (0 to 15); CI : in std_logic; SUM : out std_logic_vector (0 to 15); CO : out std_logic); end adder_DW01_add_16_0; architecture SYN of adder_DW01_add_16_0 is component EO3P port( A, B, C : in std_logic; Z : out std_logic); end component; component FA1A port( CI, A, B : in std_logic; S, CO : out std_logic); end component; component AN2 port( A, B : in std_logic; Z : out std_logic); end component; component EO port( A, B : in std_logic; Z : out std_logic); end component; signal carry_9_port, carry_4_port, carry_2_port, carry_15_port, carry_13_port, carry_6_port, carry_14_port, carry_11_port, carry_10_port, carry_12_port, carry_8_port, carry_7_port, carry_3_port, carry_5_port, carry_1_port : std_logic; begin U1_15 : EO3P port map( A => A(0), B => B(0), C => carry_15_port, Z => SUM(0) ); U1_14 : FA1A port map( CI => carry_14_port, A => A(1), B => B(1), S => SUM(1), CO => carry_15_port); U1_13 : FA1A port map( CI => carry_13_port, A => A(2), B => B(2), S => SUM(2), CO => carry_14_port); U1_12 : FA1A port map( CI => carry_12_port, A => A(3), B => B(3), S => SUM(3), CO => carry_13_port); U1_11 : FA1A port map( CI => carry_11_port, A => A(4), B => B(4), S => SUM(4), CO => carry_12_port); U1_10 : FA1A port map( CI => carry_10_port, A => A(5), B => B(5), S => SUM(5), CO => carry_11_port); U1_9 : FA1A port map( CI => carry_9_port, A => A(6), B => B(6), S => SUM(6), CO => carry_10_port); U1_8 : FA1A port map( CI => carry_8_port, A => A(7), B => B(7), S => SUM(7), CO => carry_9_port); U1_7 : FA1A port map( CI => carry_7_port, A => A(8), B => B(8), S => SUM(8), CO => carry_8_port); U1_6 : FA1A port map( CI => carry_6_port, A => A(9), B => B(9), S => SUM(9), CO => carry_7_port); U1_5 : FA1A port map( CI => carry_5_port, A => A(10), B => B(10), S => SUM(10), CO => carry_6_port); U1_4 : FA1A port map( CI => carry_4_port, A => A(11), B => B(11), S => SUM(11), CO => carry_5_port); U1_3 : FA1A port map( CI => carry_3_port, A => A(12), B => B(12), S => SUM(12), CO => carry_4_port); U1_2 : FA1A port map( CI => carry_2_port, A => A(13), B => B(13), S => SUM(13), CO => carry_3_port); U1_1 : FA1A port map( CI => carry_1_port, A => A(14), B => B(14), S => SUM(14), CO => carry_2_port); U4 : AN2 port map( A => B(15), B => A(15), Z => carry_1_port); U5 : EO port map( A => A(15), B => B(15), Z => SUM(15)); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity adder is port( A, B : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 15)); end adder; architecture SYN of adder is component adder_DW01_add_16_0 port( A, B : in std_logic_vector (0 to 15); CI : in std_logic; SUM : out std_logic_vector (0 to 15); CO : out std_logic); end component; signal n83 : std_logic; begin add_23_plus_plus : adder_DW01_add_16_0 port map( A(0) => A(0), A(1) => A(1), A(2) => A(2), A(3) => A(3), A(4) => A(4), A(5) => A(5), A(6) => A(6), A(7) => A(7), A(8) => A(8), A(9) => A(9), A(10) => A(10), A(11) => A(11), A(12) => A(12), A(13) => A(13), A(14) => A(14), A(15) => A(15), B(0) => B(0), B(1) => B(1), B(2) => B(2), B(3) => B(3), B(4) => B(4), B(5) => B(5), B(6) => B(6), B(7) => B(7), B(8) => B(8), B(9) => B(9), B(10) => B(10), B(11) => B(11), B(12) => B(12), B(13) => B(13), B(14) => B(14), B(15) => B(15), CI => n83, SUM(0) => O(0), SUM(1) => O(1), SUM(2) => O(2), SUM(3) => O(3), SUM(4) => O(4), SUM(5) => O(5) , SUM(6) => O(6), SUM(7) => O(7), SUM(8) => O(8), SUM(9) => O(9), SUM(10) => O(10), SUM(11) => O(11), SUM(12) => O(12), SUM(13) => O(13), SUM(14) => O(14) , SUM(15) => O(15), CO => open); n83 <= '0'; end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity cat is port( A : in std_logic_vector (0 to 8); B : in std_logic_vector (0 to 6); O : out std_logic_vector (0 to 15)); end cat; architecture SYN of cat is begin O <= ( B(0), B(1), B(2), B(3), B(4), B(5), B(6), A(0), A(1), A(2), A(3), A(4), A(5), A(6), A(7), A(8) ); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity increment_DW01_inc_16_0 is port( A : in std_logic_vector (0 to 15); SUM : out std_logic_vector (0 to 15)); end increment_DW01_inc_16_0; architecture SYN of increment_DW01_inc_16_0 is component HA1 port( A, B : in std_logic; S, CO : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component EO port( A, B : in std_logic; Z : out std_logic); end component; signal carry_9_port, carry_4_port, carry_2_port, carry_6_port, carry_13_port , carry_15_port, carry_11_port, carry_10_port, carry_14_port, carry_12_port, carry_7_port, carry_3_port, carry_8_port, carry_5_port : std_logic; begin U1_1_14 : HA1 port map( A => A(1), B => carry_14_port, S => SUM(1), CO => carry_15_port); U1_1_13 : HA1 port map( A => A(2), B => carry_13_port, S => SUM(2), CO => carry_14_port); U1_1_12 : HA1 port map( A => A(3), B => carry_12_port, S => SUM(3), CO => carry_13_port); U1_1_11 : HA1 port map( A => A(4), B => carry_11_port, S => SUM(4), CO => carry_12_port); U1_1_10 : HA1 port map( A => A(5), B => carry_10_port, S => SUM(5), CO => carry_11_port); U1_1_9 : HA1 port map( A => A(6), B => carry_9_port, S => SUM(6), CO => carry_10_port); U1_1_8 : HA1 port map( A => A(7), B => carry_8_port, S => SUM(7), CO => carry_9_port); U1_1_7 : HA1 port map( A => A(8), B => carry_7_port, S => SUM(8), CO => carry_8_port); U1_1_6 : HA1 port map( A => A(9), B => carry_6_port, S => SUM(9), CO => carry_7_port); U1_1_5 : HA1 port map( A => A(10), B => carry_5_port, S => SUM(10), CO => carry_6_port); U1_1_4 : HA1 port map( A => A(11), B => carry_4_port, S => SUM(11), CO => carry_5_port); U1_1_3 : HA1 port map( A => A(12), B => carry_3_port, S => SUM(12), CO => carry_4_port); U1_1_2 : HA1 port map( A => A(13), B => carry_2_port, S => SUM(13), CO => carry_3_port); U1_1_1 : HA1 port map( A => A(14), B => A(15), S => SUM(14), CO => carry_2_port); U5 : IV port map( A => A(15), Z => SUM(15)); U6 : EO port map( A => A(0), B => carry_15_port, Z => SUM(0)); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity increment is port( data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 15)); end increment; architecture SYN of increment is component increment_DW01_inc_16_0 port( A : in std_logic_vector (0 to 15); SUM : out std_logic_vector (0 to 15)); end component; begin add_95_plus_plus : increment_DW01_inc_16_0 port map( A(0) => data(0), A(1) => data(1), A(2) => data(2), A(3) => data(3), A(4) => data(4), A(5) => data(5), A(6) => data(6), A(7) => data(7), A(8) => data(8), A(9) => data(9), A(10) => data(10), A(11) => data(11), A(12) => data(12), A(13) => data(13), A(14) => data(14), A(15) => data(15), SUM(0) => O(0), SUM(1) => O(1), SUM(2) => O(2), SUM(3) => O(3), SUM(4) => O(4), SUM(5) => O(5) , SUM(6) => O(6), SUM(7) => O(7), SUM(8) => O(8), SUM(9) => O(9), SUM(10) => O(10), SUM(11) => O(11), SUM(12) => O(12), SUM(13) => O(13), SUM(14) => O(14) , SUM(15) => O(15)); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity mux2_0 is port( a, b : in std_logic_vector (0 to 15); s : in std_logic; mux2output : out std_logic_vector (0 to 15)); end mux2_0; architecture SYN of mux2_0 is component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; signal n5, n6, n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, n437, n438, n439, n440, n441 : std_logic; begin U10 : AO2 port map( A => b(6), B => n6, C => a(6), D => s, Z => n5); U11 : AO2 port map( A => b(7), B => n6, C => a(7), D => s, Z => n427); U12 : AO2 port map( A => b(8), B => n6, C => a(8), D => s, Z => n428); U13 : AO2 port map( A => b(9), B => n6, C => a(9), D => s, Z => n429); U14 : AO2 port map( A => b(10), B => n6, C => a(10), D => s, Z => n430); U15 : AO2 port map( A => b(11), B => n6, C => a(11), D => s, Z => n431); U16 : AO2 port map( A => b(12), B => n6, C => a(12), D => s, Z => n432); U17 : AO2 port map( A => b(13), B => n6, C => a(13), D => s, Z => n433); U18 : AO2 port map( A => b(14), B => n6, C => a(14), D => s, Z => n434); U19 : AO2 port map( A => b(0), B => n6, C => a(0), D => s, Z => n435); U20 : AO2 port map( A => b(1), B => n6, C => a(1), D => s, Z => n436); U21 : AO2 port map( A => b(2), B => n6, C => a(2), D => s, Z => n437); U22 : AO2 port map( A => b(3), B => n6, C => a(3), D => s, Z => n438); U23 : AO2 port map( A => b(4), B => n6, C => a(4), D => s, Z => n439); U24 : AO2 port map( A => b(5), B => n6, C => a(5), D => s, Z => n440); U25 : AO2 port map( A => b(15), B => n6, C => a(15), D => s, Z => n441); U26 : IV port map( A => s, Z => n6); U27 : IV port map( A => n5, Z => mux2output(6)); U28 : IV port map( A => n427, Z => mux2output(7)); U29 : IV port map( A => n428, Z => mux2output(8)); U30 : IV port map( A => n429, Z => mux2output(9)); U31 : IV port map( A => n430, Z => mux2output(10)); U32 : IV port map( A => n431, Z => mux2output(11)); U33 : IV port map( A => n432, Z => mux2output(12)); U34 : IV port map( A => n433, Z => mux2output(13)); U35 : IV port map( A => n434, Z => mux2output(14)); U36 : IV port map( A => n435, Z => mux2output(0)); U37 : IV port map( A => n436, Z => mux2output(1)); U38 : IV port map( A => n437, Z => mux2output(2)); U39 : IV port map( A => n438, Z => mux2output(3)); U40 : IV port map( A => n439, Z => mux2output(4)); U41 : IV port map( A => n440, Z => mux2output(5)); U42 : IV port map( A => n441, Z => mux2output(15)); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity mux2_1 is port( a, b : in std_logic_vector (0 to 15); s : in std_logic; mux2output : out std_logic_vector (0 to 15)); end mux2_1; architecture SYN of mux2_1 is component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; signal n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123 : std_logic; begin U10 : AO2 port map( A => b(6), B => n1108, C => a(6), D => s, Z => n1107); U11 : AO2 port map( A => b(7), B => n1108, C => a(7), D => s, Z => n1109); U12 : AO2 port map( A => b(8), B => n1108, C => a(8), D => s, Z => n1110); U13 : AO2 port map( A => b(9), B => n1108, C => a(9), D => s, Z => n1111); U14 : AO2 port map( A => b(10), B => n1108, C => a(10), D => s, Z => n1112); U15 : AO2 port map( A => b(11), B => n1108, C => a(11), D => s, Z => n1113); U16 : AO2 port map( A => b(12), B => n1108, C => a(12), D => s, Z => n1114); U17 : AO2 port map( A => b(13), B => n1108, C => a(13), D => s, Z => n1115); U18 : AO2 port map( A => b(14), B => n1108, C => a(14), D => s, Z => n1116); U19 : AO2 port map( A => b(0), B => n1108, C => a(0), D => s, Z => n1117); U20 : AO2 port map( A => b(1), B => n1108, C => a(1), D => s, Z => n1118); U21 : AO2 port map( A => b(2), B => n1108, C => a(2), D => s, Z => n1119); U22 : AO2 port map( A => b(3), B => n1108, C => a(3), D => s, Z => n1120); U23 : AO2 port map( A => b(4), B => n1108, C => a(4), D => s, Z => n1121); U24 : AO2 port map( A => b(5), B => n1108, C => a(5), D => s, Z => n1122); U25 : AO2 port map( A => b(15), B => n1108, C => a(15), D => s, Z => n1123); U26 : IV port map( A => s, Z => n1108); U27 : IV port map( A => n1107, Z => mux2output(6)); U28 : IV port map( A => n1109, Z => mux2output(7)); U29 : IV port map( A => n1110, Z => mux2output(8)); U30 : IV port map( A => n1111, Z => mux2output(9)); U31 : IV port map( A => n1112, Z => mux2output(10)); U32 : IV port map( A => n1113, Z => mux2output(11)); U33 : IV port map( A => n1114, Z => mux2output(12)); U34 : IV port map( A => n1115, Z => mux2output(13)); U35 : IV port map( A => n1116, Z => mux2output(14)); U36 : IV port map( A => n1117, Z => mux2output(0)); U37 : IV port map( A => n1118, Z => mux2output(1)); U38 : IV port map( A => n1119, Z => mux2output(2)); U39 : IV port map( A => n1120, Z => mux2output(3)); U40 : IV port map( A => n1121, Z => mux2output(4)); U41 : IV port map( A => n1122, Z => mux2output(5)); U42 : IV port map( A => n1123, Z => mux2output(15)); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity mux4_0 is port( c, d, e, f : in std_logic_vector (0 to 15); s : in std_logic_vector (0 to 1); muxoutput : out std_logic_vector (0 to 15)); end mux4_0; architecture SYN of mux4_0 is component ND2 port( A, B : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35 , n36, n37, n38, n39, n40, n41, n42, n43, n44 : std_logic; begin U10 : ND2 port map( A => n7, B => n8, Z => muxoutput(15)); U11 : ND2 port map( A => n9, B => n10, Z => muxoutput(14)); U12 : ND2 port map( A => n11, B => n12, Z => muxoutput(13)); U13 : ND2 port map( A => n13, B => n14, Z => muxoutput(12)); U14 : ND2 port map( A => n15, B => n16, Z => muxoutput(11)); U15 : ND2 port map( A => n17, B => n18, Z => muxoutput(10)); U16 : ND2 port map( A => n19, B => n20, Z => muxoutput(9)); U17 : ND2 port map( A => n21, B => n22, Z => muxoutput(8)); U18 : ND2 port map( A => n23, B => n24, Z => muxoutput(7)); U19 : ND2 port map( A => n25, B => n26, Z => muxoutput(6)); U20 : ND2 port map( A => n27, B => n28, Z => muxoutput(5)); U21 : ND2 port map( A => n29, B => n30, Z => muxoutput(4)); U22 : ND2 port map( A => n31, B => n32, Z => muxoutput(3)); U23 : ND2 port map( A => n33, B => n34, Z => muxoutput(2)); U24 : ND2 port map( A => n35, B => n36, Z => muxoutput(1)); U25 : ND2 port map( A => n37, B => n38, Z => muxoutput(0)); U26 : IV port map( A => s(1), Z => n39); U27 : NR2 port map( A => n41, B => n39, Z => n40); U28 : NR2 port map( A => n41, B => s(1), Z => n42); U29 : NR2 port map( A => n39, B => s(0), Z => n43); U30 : NR2 port map( A => s(1), B => s(0), Z => n44); U31 : AO2 port map( A => n40, B => f(6), C => n42, D => e(6), Z => n26); U32 : AO2 port map( A => n43, B => d(6), C => n44, D => c(6), Z => n25); U33 : AO2 port map( A => f(7), B => n40, C => e(7), D => n42, Z => n24); U34 : AO2 port map( A => d(7), B => n43, C => c(7), D => n44, Z => n23); U35 : AO2 port map( A => f(8), B => n40, C => e(8), D => n42, Z => n22); U36 : AO2 port map( A => d(8), B => n43, C => c(8), D => n44, Z => n21); U37 : AO2 port map( A => f(9), B => n40, C => e(9), D => n42, Z => n20); U38 : AO2 port map( A => d(9), B => n43, C => c(9), D => n44, Z => n19); U39 : AO2 port map( A => f(10), B => n40, C => e(10), D => n42, Z => n18); U40 : AO2 port map( A => d(10), B => n43, C => c(10), D => n44, Z => n17); U41 : AO2 port map( A => f(11), B => n40, C => e(11), D => n42, Z => n16); U42 : AO2 port map( A => d(11), B => n43, C => c(11), D => n44, Z => n15); U43 : AO2 port map( A => f(12), B => n40, C => e(12), D => n42, Z => n14); U44 : AO2 port map( A => d(12), B => n43, C => c(12), D => n44, Z => n13); U45 : AO2 port map( A => f(13), B => n40, C => e(13), D => n42, Z => n12); U46 : AO2 port map( A => d(13), B => n43, C => c(13), D => n44, Z => n11); U47 : AO2 port map( A => f(14), B => n40, C => e(14), D => n42, Z => n10); U48 : AO2 port map( A => d(14), B => n43, C => c(14), D => n44, Z => n9); U49 : AO2 port map( A => f(0), B => n40, C => e(0), D => n42, Z => n38); U50 : AO2 port map( A => d(0), B => n43, C => c(0), D => n44, Z => n37); U51 : AO2 port map( A => f(1), B => n40, C => e(1), D => n42, Z => n36); U52 : AO2 port map( A => d(1), B => n43, C => c(1), D => n44, Z => n35); U53 : AO2 port map( A => f(2), B => n40, C => e(2), D => n42, Z => n34); U54 : AO2 port map( A => d(2), B => n43, C => c(2), D => n44, Z => n33); U55 : AO2 port map( A => f(3), B => n40, C => e(3), D => n42, Z => n32); U56 : AO2 port map( A => d(3), B => n43, C => c(3), D => n44, Z => n31); U57 : AO2 port map( A => f(4), B => n40, C => e(4), D => n42, Z => n30); U58 : AO2 port map( A => d(4), B => n43, C => c(4), D => n44, Z => n29); U59 : AO2 port map( A => f(5), B => n40, C => e(5), D => n42, Z => n28); U60 : AO2 port map( A => d(5), B => n43, C => c(5), D => n44, Z => n27); U61 : AO2 port map( A => f(15), B => n40, C => e(15), D => n42, Z => n8); U62 : AO2 port map( A => d(15), B => n43, C => c(15), D => n44, Z => n7); U63 : IV port map( A => s(0), Z => n41); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity mux4_1 is port( c, d, e, f : in std_logic_vector (0 to 15); s : in std_logic_vector (0 to 1); muxoutput : out std_logic_vector (0 to 15)); end mux4_1; architecture SYN of mux4_1 is component ND2 port( A, B : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73 , n74, n75, n76, n77, n78, n79, n80, n81, n82 : std_logic; begin U10 : ND2 port map( A => n45, B => n46, Z => muxoutput(15)); U11 : ND2 port map( A => n47, B => n48, Z => muxoutput(14)); U12 : ND2 port map( A => n49, B => n50, Z => muxoutput(13)); U13 : ND2 port map( A => n51, B => n52, Z => muxoutput(12)); U14 : ND2 port map( A => n53, B => n54, Z => muxoutput(11)); U15 : ND2 port map( A => n55, B => n56, Z => muxoutput(10)); U16 : ND2 port map( A => n57, B => n58, Z => muxoutput(9)); U17 : ND2 port map( A => n59, B => n60, Z => muxoutput(8)); U18 : ND2 port map( A => n61, B => n62, Z => muxoutput(7)); U19 : ND2 port map( A => n63, B => n64, Z => muxoutput(6)); U20 : ND2 port map( A => n65, B => n66, Z => muxoutput(5)); U21 : ND2 port map( A => n67, B => n68, Z => muxoutput(4)); U22 : ND2 port map( A => n69, B => n70, Z => muxoutput(3)); U23 : ND2 port map( A => n71, B => n72, Z => muxoutput(2)); U24 : ND2 port map( A => n73, B => n74, Z => muxoutput(1)); U25 : ND2 port map( A => n75, B => n76, Z => muxoutput(0)); U26 : IV port map( A => s(1), Z => n77); U27 : NR2 port map( A => n79, B => n77, Z => n78); U28 : NR2 port map( A => n79, B => s(1), Z => n80); U29 : NR2 port map( A => n77, B => s(0), Z => n81); U30 : NR2 port map( A => s(1), B => s(0), Z => n82); U31 : AO2 port map( A => n78, B => f(6), C => n80, D => e(6), Z => n64); U32 : AO2 port map( A => n81, B => d(6), C => n82, D => c(6), Z => n63); U33 : AO2 port map( A => f(7), B => n78, C => e(7), D => n80, Z => n62); U34 : AO2 port map( A => d(7), B => n81, C => c(7), D => n82, Z => n61); U35 : AO2 port map( A => f(8), B => n78, C => e(8), D => n80, Z => n60); U36 : AO2 port map( A => d(8), B => n81, C => c(8), D => n82, Z => n59); U37 : AO2 port map( A => f(9), B => n78, C => e(9), D => n80, Z => n58); U38 : AO2 port map( A => d(9), B => n81, C => c(9), D => n82, Z => n57); U39 : AO2 port map( A => f(10), B => n78, C => e(10), D => n80, Z => n56); U40 : AO2 port map( A => d(10), B => n81, C => c(10), D => n82, Z => n55); U41 : AO2 port map( A => f(11), B => n78, C => e(11), D => n80, Z => n54); U42 : AO2 port map( A => d(11), B => n81, C => c(11), D => n82, Z => n53); U43 : AO2 port map( A => f(12), B => n78, C => e(12), D => n80, Z => n52); U44 : AO2 port map( A => d(12), B => n81, C => c(12), D => n82, Z => n51); U45 : AO2 port map( A => f(13), B => n78, C => e(13), D => n80, Z => n50); U46 : AO2 port map( A => d(13), B => n81, C => c(13), D => n82, Z => n49); U47 : AO2 port map( A => f(14), B => n78, C => e(14), D => n80, Z => n48); U48 : AO2 port map( A => d(14), B => n81, C => c(14), D => n82, Z => n47); U49 : AO2 port map( A => f(0), B => n78, C => e(0), D => n80, Z => n76); U50 : AO2 port map( A => d(0), B => n81, C => c(0), D => n82, Z => n75); U51 : AO2 port map( A => f(1), B => n78, C => e(1), D => n80, Z => n74); U52 : AO2 port map( A => d(1), B => n81, C => c(1), D => n82, Z => n73); U53 : AO2 port map( A => f(2), B => n78, C => e(2), D => n80, Z => n72); U54 : AO2 port map( A => d(2), B => n81, C => c(2), D => n82, Z => n71); U55 : AO2 port map( A => f(3), B => n78, C => e(3), D => n80, Z => n70); U56 : AO2 port map( A => d(3), B => n81, C => c(3), D => n82, Z => n69); U57 : AO2 port map( A => f(4), B => n78, C => e(4), D => n80, Z => n68); U58 : AO2 port map( A => d(4), B => n81, C => c(4), D => n82, Z => n67); U59 : AO2 port map( A => f(5), B => n78, C => e(5), D => n80, Z => n66); U60 : AO2 port map( A => d(5), B => n81, C => c(5), D => n82, Z => n65); U61 : AO2 port map( A => f(15), B => n78, C => e(15), D => n80, Z => n46); U62 : AO2 port map( A => d(15), B => n81, C => c(15), D => n82, Z => n45); U63 : IV port map( A => s(0), Z => n79); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity mux4_2 is port( c, d, e, f : in std_logic_vector (0 to 15); s : in std_logic_vector (0 to 1); muxoutput : out std_logic_vector (0 to 15)); end mux4_2; architecture SYN of mux4_2 is component ND2 port( A, B : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal n561, n562, n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, n593, n594, n595, n596, n597, n598 : std_logic; begin U10 : ND2 port map( A => n561, B => n562, Z => muxoutput(15)); U11 : ND2 port map( A => n563, B => n564, Z => muxoutput(14)); U12 : ND2 port map( A => n565, B => n566, Z => muxoutput(13)); U13 : ND2 port map( A => n567, B => n568, Z => muxoutput(12)); U14 : ND2 port map( A => n569, B => n570, Z => muxoutput(11)); U15 : ND2 port map( A => n571, B => n572, Z => muxoutput(10)); U16 : ND2 port map( A => n573, B => n574, Z => muxoutput(9)); U17 : ND2 port map( A => n575, B => n576, Z => muxoutput(8)); U18 : ND2 port map( A => n577, B => n578, Z => muxoutput(7)); U19 : ND2 port map( A => n579, B => n580, Z => muxoutput(6)); U20 : ND2 port map( A => n581, B => n582, Z => muxoutput(5)); U21 : ND2 port map( A => n583, B => n584, Z => muxoutput(4)); U22 : ND2 port map( A => n585, B => n586, Z => muxoutput(3)); U23 : ND2 port map( A => n587, B => n588, Z => muxoutput(2)); U24 : ND2 port map( A => n589, B => n590, Z => muxoutput(1)); U25 : ND2 port map( A => n591, B => n592, Z => muxoutput(0)); U26 : IV port map( A => s(1), Z => n593); U27 : NR2 port map( A => n595, B => n593, Z => n594); U28 : NR2 port map( A => n595, B => s(1), Z => n596); U29 : NR2 port map( A => n593, B => s(0), Z => n597); U30 : NR2 port map( A => s(1), B => s(0), Z => n598); U31 : AO2 port map( A => n594, B => f(6), C => n596, D => e(6), Z => n580); U32 : AO2 port map( A => n597, B => d(6), C => n598, D => c(6), Z => n579); U33 : AO2 port map( A => f(7), B => n594, C => e(7), D => n596, Z => n578); U34 : AO2 port map( A => d(7), B => n597, C => c(7), D => n598, Z => n577); U35 : AO2 port map( A => f(8), B => n594, C => e(8), D => n596, Z => n576); U36 : AO2 port map( A => d(8), B => n597, C => c(8), D => n598, Z => n575); U37 : AO2 port map( A => f(9), B => n594, C => e(9), D => n596, Z => n574); U38 : AO2 port map( A => d(9), B => n597, C => c(9), D => n598, Z => n573); U39 : AO2 port map( A => f(10), B => n594, C => e(10), D => n596, Z => n572) ; U40 : AO2 port map( A => d(10), B => n597, C => c(10), D => n598, Z => n571) ; U41 : AO2 port map( A => f(11), B => n594, C => e(11), D => n596, Z => n570) ; U42 : AO2 port map( A => d(11), B => n597, C => c(11), D => n598, Z => n569) ; U43 : AO2 port map( A => f(12), B => n594, C => e(12), D => n596, Z => n568) ; U44 : AO2 port map( A => d(12), B => n597, C => c(12), D => n598, Z => n567) ; U45 : AO2 port map( A => f(13), B => n594, C => e(13), D => n596, Z => n566) ; U46 : AO2 port map( A => d(13), B => n597, C => c(13), D => n598, Z => n565) ; U47 : AO2 port map( A => f(14), B => n594, C => e(14), D => n596, Z => n564) ; U48 : AO2 port map( A => d(14), B => n597, C => c(14), D => n598, Z => n563) ; U49 : AO2 port map( A => f(0), B => n594, C => e(0), D => n596, Z => n592); U50 : AO2 port map( A => d(0), B => n597, C => c(0), D => n598, Z => n591); U51 : AO2 port map( A => f(1), B => n594, C => e(1), D => n596, Z => n590); U52 : AO2 port map( A => d(1), B => n597, C => c(1), D => n598, Z => n589); U53 : AO2 port map( A => f(2), B => n594, C => e(2), D => n596, Z => n588); U54 : AO2 port map( A => d(2), B => n597, C => c(2), D => n598, Z => n587); U55 : AO2 port map( A => f(3), B => n594, C => e(3), D => n596, Z => n586); U56 : AO2 port map( A => d(3), B => n597, C => c(3), D => n598, Z => n585); U57 : AO2 port map( A => f(4), B => n594, C => e(4), D => n596, Z => n584); U58 : AO2 port map( A => d(4), B => n597, C => c(4), D => n598, Z => n583); U59 : AO2 port map( A => f(5), B => n594, C => e(5), D => n596, Z => n582); U60 : AO2 port map( A => d(5), B => n597, C => c(5), D => n598, Z => n581); U61 : AO2 port map( A => f(15), B => n594, C => e(15), D => n596, Z => n562) ; U62 : AO2 port map( A => d(15), B => n597, C => c(15), D => n598, Z => n561) ; U63 : IV port map( A => s(0), Z => n595); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity reg_0 is port( clk, load : in std_logic; data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 15); clear : in std_logic); end reg_0; architecture SYN of reg_0 is component FJK2S port( J, K, CP, CD, TI, TE : in std_logic; Q, QN : out std_logic); end component; component FD1 port( D, CP : in std_logic; Q, QN : out std_logic); end component; component AO7 port( A, B, C : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component AN2 port( A, B : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal temp_2_port, O39_1_port, O39_8_port, temp_6_port, O39_5_port, temp_4_port, temp_9_port, O39_7_port, O39_3_port, temp_0_port, O39_11_port, temp_10_port, temp_14_port, O39_15_port, temp_12_port, O39_13_port, temp_13_port, O39_12_port, temp_15_port, O39_14_port, temp_11_port, O39_10_port, temp_8_port, O39_2_port, temp_1_port, temp_5_port, O39_6_port, O39_4_port, temp_7_port, temp_3_port, O39_0_port , O39_9_port, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, n136 : std_logic; begin temp_reg_15_label : FJK2S port map( J => n104, K => n104, CP => clk, CD => n119, TI => data(0), TE => load, Q => temp_15_port, QN => open); temp_reg_14_label : FJK2S port map( J => n105, K => n105, CP => clk, CD => n119, TI => data(1), TE => load, Q => temp_14_port, QN => open); temp_reg_13_label : FJK2S port map( J => n106, K => n106, CP => clk, CD => n119, TI => data(2), TE => load, Q => temp_13_port, QN => open); temp_reg_12_label : FJK2S port map( J => n107, K => n107, CP => clk, CD => n119, TI => data(3), TE => load, Q => temp_12_port, QN => open); temp_reg_11_label : FJK2S port map( J => n108, K => n108, CP => clk, CD => n119, TI => data(4), TE => load, Q => temp_11_port, QN => open); temp_reg_10_label : FJK2S port map( J => n109, K => n109, CP => clk, CD => n119, TI => data(5), TE => load, Q => temp_10_port, QN => open); temp_reg_9_label : FJK2S port map( J => n110, K => n110, CP => clk, CD => n119, TI => data(6), TE => load, Q => temp_9_port, QN => open); temp_reg_8_label : FJK2S port map( J => n111, K => n111, CP => clk, CD => n119, TI => data(7), TE => load, Q => temp_8_port, QN => open); temp_reg_7_label : FJK2S port map( J => n112, K => n112, CP => clk, CD => n119, TI => data(8), TE => load, Q => temp_7_port, QN => open); temp_reg_6_label : FJK2S port map( J => n113, K => n113, CP => clk, CD => n119, TI => data(9), TE => load, Q => temp_6_port, QN => open); temp_reg_5_label : FJK2S port map( J => n114, K => n114, CP => clk, CD => n119, TI => data(10), TE => load, Q => temp_5_port, QN => open); temp_reg_4_label : FJK2S port map( J => n115, K => n115, CP => clk, CD => n119, TI => data(11), TE => load, Q => temp_4_port, QN => open); temp_reg_3_label : FJK2S port map( J => n116, K => n116, CP => clk, CD => n119, TI => data(12), TE => load, Q => temp_3_port, QN => open); temp_reg_2_label : FJK2S port map( J => n117, K => n117, CP => clk, CD => n119, TI => data(13), TE => load, Q => temp_2_port, QN => open); temp_reg_1_label : FJK2S port map( J => n118, K => n118, CP => clk, CD => n119, TI => data(14), TE => load, Q => temp_1_port, QN => open); temp_reg_0_label : FJK2S port map( J => n120, K => n120, CP => clk, CD => n119, TI => data(15), TE => load, Q => temp_0_port, QN => open); O_reg_15_label : FD1 port map( D => O39_15_port, CP => clk, Q => O(0), QN => n121); O_reg_14_label : FD1 port map( D => O39_14_port, CP => clk, Q => O(1), QN => n122); O_reg_13_label : FD1 port map( D => O39_13_port, CP => clk, Q => O(2), QN => n123); O_reg_12_label : FD1 port map( D => O39_12_port, CP => clk, Q => O(3), QN => n124); O_reg_11_label : FD1 port map( D => O39_11_port, CP => clk, Q => O(4), QN => n125); O_reg_10_label : FD1 port map( D => O39_10_port, CP => clk, Q => O(5), QN => n126); O_reg_9_label : FD1 port map( D => O39_9_port, CP => clk, Q => O(6), QN => n127); O_reg_8_label : FD1 port map( D => O39_8_port, CP => clk, Q => O(7), QN => n128); O_reg_7_label : FD1 port map( D => O39_7_port, CP => clk, Q => O(8), QN => n129); O_reg_6_label : FD1 port map( D => O39_6_port, CP => clk, Q => O(9), QN => n130); O_reg_5_label : FD1 port map( D => O39_5_port, CP => clk, Q => O(10), QN => n131); O_reg_4_label : FD1 port map( D => O39_4_port, CP => clk, Q => O(11), QN => n132); O_reg_3_label : FD1 port map( D => O39_3_port, CP => clk, Q => O(12), QN => n133); O_reg_2_label : FD1 port map( D => O39_2_port, CP => clk, Q => O(13), QN => n134); O_reg_1_label : FD1 port map( D => O39_1_port, CP => clk, Q => O(14), QN => n135); O_reg_0_label : FD1 port map( D => O39_0_port, CP => clk, Q => O(15), QN => n136); U38 : AO7 port map( A => n119, B => n121, C => n86, Z => O39_15_port); U39 : AO7 port map( A => n119, B => n122, C => n87, Z => O39_14_port); U40 : AO7 port map( A => n119, B => n123, C => n88, Z => O39_13_port); U41 : AO7 port map( A => n119, B => n124, C => n89, Z => O39_12_port); U42 : AO7 port map( A => n119, B => n125, C => n90, Z => O39_11_port); U43 : AO7 port map( A => n119, B => n126, C => n91, Z => O39_10_port); U44 : AO7 port map( A => n119, B => n127, C => n92, Z => O39_9_port); U45 : AO7 port map( A => n119, B => n128, C => n93, Z => O39_8_port); U46 : AO7 port map( A => n119, B => n129, C => n94, Z => O39_7_port); U47 : AO7 port map( A => n119, B => n130, C => n95, Z => O39_6_port); U48 : AO7 port map( A => n119, B => n131, C => n96, Z => O39_5_port); U49 : AO7 port map( A => n119, B => n132, C => n97, Z => O39_4_port); U50 : AO7 port map( A => n119, B => n133, C => n98, Z => O39_3_port); U51 : AO7 port map( A => n119, B => n134, C => n99, Z => O39_2_port); U52 : AO7 port map( A => n119, B => n135, C => n100, Z => O39_1_port); U53 : AO7 port map( A => n119, B => n136, C => n101, Z => O39_0_port); U54 : IV port map( A => clear, Z => n119); U55 : NR2 port map( A => clear, B => load, Z => n102); U56 : AN2 port map( A => load, B => n119, Z => n103); U57 : AO2 port map( A => temp_9_port, B => n102, C => data(6), D => n103, Z => n92); U58 : AO2 port map( A => temp_8_port, B => n102, C => data(7), D => n103, Z => n93); U59 : AO2 port map( A => temp_7_port, B => n102, C => data(8), D => n103, Z => n94); U60 : AO2 port map( A => temp_6_port, B => n102, C => data(9), D => n103, Z => n95); U61 : AO2 port map( A => temp_5_port, B => n102, C => data(10), D => n103, Z => n96); U62 : AO2 port map( A => temp_4_port, B => n102, C => data(11), D => n103, Z => n97); U63 : AO2 port map( A => temp_3_port, B => n102, C => data(12), D => n103, Z => n98); U64 : AO2 port map( A => temp_2_port, B => n102, C => data(13), D => n103, Z => n99); U65 : AO2 port map( A => temp_1_port, B => n102, C => data(14), D => n103, Z => n100); U66 : AO2 port map( A => temp_15_port, B => n102, C => data(0), D => n103, Z => n86); U67 : AO2 port map( A => temp_14_port, B => n102, C => data(1), D => n103, Z => n87); U68 : AO2 port map( A => temp_13_port, B => n102, C => data(2), D => n103, Z => n88); U69 : AO2 port map( A => temp_12_port, B => n102, C => data(3), D => n103, Z => n89); U70 : AO2 port map( A => temp_11_port, B => n102, C => data(4), D => n103, Z => n90); U71 : AO2 port map( A => temp_10_port, B => n102, C => data(5), D => n103, Z => n91); U72 : AO2 port map( A => temp_0_port, B => n102, C => data(15), D => n103, Z => n101); n104 <= '0'; n105 <= '0'; n106 <= '0'; n107 <= '0'; n108 <= '0'; n109 <= '0'; n110 <= '0'; n111 <= '0'; n112 <= '0'; n113 <= '0'; n114 <= '0'; n115 <= '0'; n116 <= '0'; n117 <= '0'; n118 <= '0'; n120 <= '0'; end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity reg_1 is port( clk, load : in std_logic; data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 15); clear : in std_logic); end reg_1; architecture SYN of reg_1 is component FJK2S port( J, K, CP, CD, TI, TE : in std_logic; Q, QN : out std_logic); end component; component FD1 port( D, CP : in std_logic; Q, QN : out std_logic); end component; component AO7 port( A, B, C : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component AN2 port( A, B : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal temp_2_port, O39_1_port, O39_8_port, temp_6_port, O39_5_port, temp_4_port, temp_9_port, O39_7_port, O39_3_port, temp_0_port, O39_11_port, temp_10_port, temp_14_port, O39_15_port, temp_12_port, O39_13_port, temp_13_port, O39_12_port, temp_15_port, O39_14_port, temp_11_port, O39_10_port, temp_8_port, O39_2_port, temp_1_port, temp_5_port, O39_6_port, O39_4_port, temp_7_port, temp_3_port, O39_0_port , O39_9_port, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185, n186, n187 : std_logic; begin temp_reg_15_label : FJK2S port map( J => n155, K => n155, CP => clk, CD => n170, TI => data(0), TE => load, Q => temp_15_port, QN => open); temp_reg_14_label : FJK2S port map( J => n156, K => n156, CP => clk, CD => n170, TI => data(1), TE => load, Q => temp_14_port, QN => open); temp_reg_13_label : FJK2S port map( J => n157, K => n157, CP => clk, CD => n170, TI => data(2), TE => load, Q => temp_13_port, QN => open); temp_reg_12_label : FJK2S port map( J => n158, K => n158, CP => clk, CD => n170, TI => data(3), TE => load, Q => temp_12_port, QN => open); temp_reg_11_label : FJK2S port map( J => n159, K => n159, CP => clk, CD => n170, TI => data(4), TE => load, Q => temp_11_port, QN => open); temp_reg_10_label : FJK2S port map( J => n160, K => n160, CP => clk, CD => n170, TI => data(5), TE => load, Q => temp_10_port, QN => open); temp_reg_9_label : FJK2S port map( J => n161, K => n161, CP => clk, CD => n170, TI => data(6), TE => load, Q => temp_9_port, QN => open); temp_reg_8_label : FJK2S port map( J => n162, K => n162, CP => clk, CD => n170, TI => data(7), TE => load, Q => temp_8_port, QN => open); temp_reg_7_label : FJK2S port map( J => n163, K => n163, CP => clk, CD => n170, TI => data(8), TE => load, Q => temp_7_port, QN => open); temp_reg_6_label : FJK2S port map( J => n164, K => n164, CP => clk, CD => n170, TI => data(9), TE => load, Q => temp_6_port, QN => open); temp_reg_5_label : FJK2S port map( J => n165, K => n165, CP => clk, CD => n170, TI => data(10), TE => load, Q => temp_5_port, QN => open); temp_reg_4_label : FJK2S port map( J => n166, K => n166, CP => clk, CD => n170, TI => data(11), TE => load, Q => temp_4_port, QN => open); temp_reg_3_label : FJK2S port map( J => n167, K => n167, CP => clk, CD => n170, TI => data(12), TE => load, Q => temp_3_port, QN => open); temp_reg_2_label : FJK2S port map( J => n168, K => n168, CP => clk, CD => n170, TI => data(13), TE => load, Q => temp_2_port, QN => open); temp_reg_1_label : FJK2S port map( J => n169, K => n169, CP => clk, CD => n170, TI => data(14), TE => load, Q => temp_1_port, QN => open); temp_reg_0_label : FJK2S port map( J => n171, K => n171, CP => clk, CD => n170, TI => data(15), TE => load, Q => temp_0_port, QN => open); O_reg_15_label : FD1 port map( D => O39_15_port, CP => clk, Q => O(0), QN => n172); O_reg_14_label : FD1 port map( D => O39_14_port, CP => clk, Q => O(1), QN => n173); O_reg_13_label : FD1 port map( D => O39_13_port, CP => clk, Q => O(2), QN => n174); O_reg_12_label : FD1 port map( D => O39_12_port, CP => clk, Q => O(3), QN => n175); O_reg_11_label : FD1 port map( D => O39_11_port, CP => clk, Q => O(4), QN => n176); O_reg_10_label : FD1 port map( D => O39_10_port, CP => clk, Q => O(5), QN => n177); O_reg_9_label : FD1 port map( D => O39_9_port, CP => clk, Q => O(6), QN => n178); O_reg_8_label : FD1 port map( D => O39_8_port, CP => clk, Q => O(7), QN => n179); O_reg_7_label : FD1 port map( D => O39_7_port, CP => clk, Q => O(8), QN => n180); O_reg_6_label : FD1 port map( D => O39_6_port, CP => clk, Q => O(9), QN => n181); O_reg_5_label : FD1 port map( D => O39_5_port, CP => clk, Q => O(10), QN => n182); O_reg_4_label : FD1 port map( D => O39_4_port, CP => clk, Q => O(11), QN => n183); O_reg_3_label : FD1 port map( D => O39_3_port, CP => clk, Q => O(12), QN => n184); O_reg_2_label : FD1 port map( D => O39_2_port, CP => clk, Q => O(13), QN => n185); O_reg_1_label : FD1 port map( D => O39_1_port, CP => clk, Q => O(14), QN => n186); O_reg_0_label : FD1 port map( D => O39_0_port, CP => clk, Q => O(15), QN => n187); U38 : AO7 port map( A => n170, B => n172, C => n137, Z => O39_15_port); U39 : AO7 port map( A => n170, B => n173, C => n138, Z => O39_14_port); U40 : AO7 port map( A => n170, B => n174, C => n139, Z => O39_13_port); U41 : AO7 port map( A => n170, B => n175, C => n140, Z => O39_12_port); U42 : AO7 port map( A => n170, B => n176, C => n141, Z => O39_11_port); U43 : AO7 port map( A => n170, B => n177, C => n142, Z => O39_10_port); U44 : AO7 port map( A => n170, B => n178, C => n143, Z => O39_9_port); U45 : AO7 port map( A => n170, B => n179, C => n144, Z => O39_8_port); U46 : AO7 port map( A => n170, B => n180, C => n145, Z => O39_7_port); U47 : AO7 port map( A => n170, B => n181, C => n146, Z => O39_6_port); U48 : AO7 port map( A => n170, B => n182, C => n147, Z => O39_5_port); U49 : AO7 port map( A => n170, B => n183, C => n148, Z => O39_4_port); U50 : AO7 port map( A => n170, B => n184, C => n149, Z => O39_3_port); U51 : AO7 port map( A => n170, B => n185, C => n150, Z => O39_2_port); U52 : AO7 port map( A => n170, B => n186, C => n151, Z => O39_1_port); U53 : AO7 port map( A => n170, B => n187, C => n152, Z => O39_0_port); U54 : IV port map( A => clear, Z => n170); U55 : NR2 port map( A => clear, B => load, Z => n153); U56 : AN2 port map( A => load, B => n170, Z => n154); U57 : AO2 port map( A => temp_9_port, B => n153, C => data(6), D => n154, Z => n143); U58 : AO2 port map( A => temp_8_port, B => n153, C => data(7), D => n154, Z => n144); U59 : AO2 port map( A => temp_7_port, B => n153, C => data(8), D => n154, Z => n145); U60 : AO2 port map( A => temp_6_port, B => n153, C => data(9), D => n154, Z => n146); U61 : AO2 port map( A => temp_5_port, B => n153, C => data(10), D => n154, Z => n147); U62 : AO2 port map( A => temp_4_port, B => n153, C => data(11), D => n154, Z => n148); U63 : AO2 port map( A => temp_3_port, B => n153, C => data(12), D => n154, Z => n149); U64 : AO2 port map( A => temp_2_port, B => n153, C => data(13), D => n154, Z => n150); U65 : AO2 port map( A => temp_1_port, B => n153, C => data(14), D => n154, Z => n151); U66 : AO2 port map( A => temp_15_port, B => n153, C => data(0), D => n154, Z => n137); U67 : AO2 port map( A => temp_14_port, B => n153, C => data(1), D => n154, Z => n138); U68 : AO2 port map( A => temp_13_port, B => n153, C => data(2), D => n154, Z => n139); U69 : AO2 port map( A => temp_12_port, B => n153, C => data(3), D => n154, Z => n140); U70 : AO2 port map( A => temp_11_port, B => n153, C => data(4), D => n154, Z => n141); U71 : AO2 port map( A => temp_10_port, B => n153, C => data(5), D => n154, Z => n142); U72 : AO2 port map( A => temp_0_port, B => n153, C => data(15), D => n154, Z => n152); n155 <= '0'; n156 <= '0'; n157 <= '0'; n158 <= '0'; n159 <= '0'; n160 <= '0'; n161 <= '0'; n162 <= '0'; n163 <= '0'; n164 <= '0'; n165 <= '0'; n166 <= '0'; n167 <= '0'; n168 <= '0'; n169 <= '0'; n171 <= '0'; end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity reg_2 is port( clk, load : in std_logic; data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 15); clear : in std_logic); end reg_2; architecture SYN of reg_2 is component FJK2S port( J, K, CP, CD, TI, TE : in std_logic; Q, QN : out std_logic); end component; component FD1 port( D, CP : in std_logic; Q, QN : out std_logic); end component; component AO7 port( A, B, C : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component AN2 port( A, B : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal temp_2_port, O39_1_port, O39_8_port, temp_6_port, O39_5_port, temp_4_port, temp_9_port, O39_7_port, O39_3_port, temp_0_port, O39_11_port, temp_10_port, temp_14_port, O39_15_port, temp_12_port, O39_13_port, temp_13_port, O39_12_port, temp_15_port, O39_14_port, temp_11_port, O39_10_port, temp_8_port, O39_2_port, temp_1_port, temp_5_port, O39_6_port, O39_4_port, temp_7_port, temp_3_port, O39_0_port , O39_9_port, n188, n189, n190, n191, n192, n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, n232, n233, n234, n235, n236, n237, n238 : std_logic; begin temp_reg_15_label : FJK2S port map( J => n206, K => n206, CP => clk, CD => n221, TI => data(0), TE => load, Q => temp_15_port, QN => open); temp_reg_14_label : FJK2S port map( J => n207, K => n207, CP => clk, CD => n221, TI => data(1), TE => load, Q => temp_14_port, QN => open); temp_reg_13_label : FJK2S port map( J => n208, K => n208, CP => clk, CD => n221, TI => data(2), TE => load, Q => temp_13_port, QN => open); temp_reg_12_label : FJK2S port map( J => n209, K => n209, CP => clk, CD => n221, TI => data(3), TE => load, Q => temp_12_port, QN => open); temp_reg_11_label : FJK2S port map( J => n210, K => n210, CP => clk, CD => n221, TI => data(4), TE => load, Q => temp_11_port, QN => open); temp_reg_10_label : FJK2S port map( J => n211, K => n211, CP => clk, CD => n221, TI => data(5), TE => load, Q => temp_10_port, QN => open); temp_reg_9_label : FJK2S port map( J => n212, K => n212, CP => clk, CD => n221, TI => data(6), TE => load, Q => temp_9_port, QN => open); temp_reg_8_label : FJK2S port map( J => n213, K => n213, CP => clk, CD => n221, TI => data(7), TE => load, Q => temp_8_port, QN => open); temp_reg_7_label : FJK2S port map( J => n214, K => n214, CP => clk, CD => n221, TI => data(8), TE => load, Q => temp_7_port, QN => open); temp_reg_6_label : FJK2S port map( J => n215, K => n215, CP => clk, CD => n221, TI => data(9), TE => load, Q => temp_6_port, QN => open); temp_reg_5_label : FJK2S port map( J => n216, K => n216, CP => clk, CD => n221, TI => data(10), TE => load, Q => temp_5_port, QN => open); temp_reg_4_label : FJK2S port map( J => n217, K => n217, CP => clk, CD => n221, TI => data(11), TE => load, Q => temp_4_port, QN => open); temp_reg_3_label : FJK2S port map( J => n218, K => n218, CP => clk, CD => n221, TI => data(12), TE => load, Q => temp_3_port, QN => open); temp_reg_2_label : FJK2S port map( J => n219, K => n219, CP => clk, CD => n221, TI => data(13), TE => load, Q => temp_2_port, QN => open); temp_reg_1_label : FJK2S port map( J => n220, K => n220, CP => clk, CD => n221, TI => data(14), TE => load, Q => temp_1_port, QN => open); temp_reg_0_label : FJK2S port map( J => n222, K => n222, CP => clk, CD => n221, TI => data(15), TE => load, Q => temp_0_port, QN => open); O_reg_15_label : FD1 port map( D => O39_15_port, CP => clk, Q => O(0), QN => n223); O_reg_14_label : FD1 port map( D => O39_14_port, CP => clk, Q => O(1), QN => n224); O_reg_13_label : FD1 port map( D => O39_13_port, CP => clk, Q => O(2), QN => n225); O_reg_12_label : FD1 port map( D => O39_12_port, CP => clk, Q => O(3), QN => n226); O_reg_11_label : FD1 port map( D => O39_11_port, CP => clk, Q => O(4), QN => n227); O_reg_10_label : FD1 port map( D => O39_10_port, CP => clk, Q => O(5), QN => n228); O_reg_9_label : FD1 port map( D => O39_9_port, CP => clk, Q => O(6), QN => n229); O_reg_8_label : FD1 port map( D => O39_8_port, CP => clk, Q => O(7), QN => n230); O_reg_7_label : FD1 port map( D => O39_7_port, CP => clk, Q => O(8), QN => n231); O_reg_6_label : FD1 port map( D => O39_6_port, CP => clk, Q => O(9), QN => n232); O_reg_5_label : FD1 port map( D => O39_5_port, CP => clk, Q => O(10), QN => n233); O_reg_4_label : FD1 port map( D => O39_4_port, CP => clk, Q => O(11), QN => n234); O_reg_3_label : FD1 port map( D => O39_3_port, CP => clk, Q => O(12), QN => n235); O_reg_2_label : FD1 port map( D => O39_2_port, CP => clk, Q => O(13), QN => n236); O_reg_1_label : FD1 port map( D => O39_1_port, CP => clk, Q => O(14), QN => n237); O_reg_0_label : FD1 port map( D => O39_0_port, CP => clk, Q => O(15), QN => n238); U38 : AO7 port map( A => n221, B => n223, C => n188, Z => O39_15_port); U39 : AO7 port map( A => n221, B => n224, C => n189, Z => O39_14_port); U40 : AO7 port map( A => n221, B => n225, C => n190, Z => O39_13_port); U41 : AO7 port map( A => n221, B => n226, C => n191, Z => O39_12_port); U42 : AO7 port map( A => n221, B => n227, C => n192, Z => O39_11_port); U43 : AO7 port map( A => n221, B => n228, C => n193, Z => O39_10_port); U44 : AO7 port map( A => n221, B => n229, C => n194, Z => O39_9_port); U45 : AO7 port map( A => n221, B => n230, C => n195, Z => O39_8_port); U46 : AO7 port map( A => n221, B => n231, C => n196, Z => O39_7_port); U47 : AO7 port map( A => n221, B => n232, C => n197, Z => O39_6_port); U48 : AO7 port map( A => n221, B => n233, C => n198, Z => O39_5_port); U49 : AO7 port map( A => n221, B => n234, C => n199, Z => O39_4_port); U50 : AO7 port map( A => n221, B => n235, C => n200, Z => O39_3_port); U51 : AO7 port map( A => n221, B => n236, C => n201, Z => O39_2_port); U52 : AO7 port map( A => n221, B => n237, C => n202, Z => O39_1_port); U53 : AO7 port map( A => n221, B => n238, C => n203, Z => O39_0_port); U54 : IV port map( A => clear, Z => n221); U55 : NR2 port map( A => clear, B => load, Z => n204); U56 : AN2 port map( A => load, B => n221, Z => n205); U57 : AO2 port map( A => temp_9_port, B => n204, C => data(6), D => n205, Z => n194); U58 : AO2 port map( A => temp_8_port, B => n204, C => data(7), D => n205, Z => n195); U59 : AO2 port map( A => temp_7_port, B => n204, C => data(8), D => n205, Z => n196); U60 : AO2 port map( A => temp_6_port, B => n204, C => data(9), D => n205, Z => n197); U61 : AO2 port map( A => temp_5_port, B => n204, C => data(10), D => n205, Z => n198); U62 : AO2 port map( A => temp_4_port, B => n204, C => data(11), D => n205, Z => n199); U63 : AO2 port map( A => temp_3_port, B => n204, C => data(12), D => n205, Z => n200); U64 : AO2 port map( A => temp_2_port, B => n204, C => data(13), D => n205, Z => n201); U65 : AO2 port map( A => temp_1_port, B => n204, C => data(14), D => n205, Z => n202); U66 : AO2 port map( A => temp_15_port, B => n204, C => data(0), D => n205, Z => n188); U67 : AO2 port map( A => temp_14_port, B => n204, C => data(1), D => n205, Z => n189); U68 : AO2 port map( A => temp_13_port, B => n204, C => data(2), D => n205, Z => n190); U69 : AO2 port map( A => temp_12_port, B => n204, C => data(3), D => n205, Z => n191); U70 : AO2 port map( A => temp_11_port, B => n204, C => data(4), D => n205, Z => n192); U71 : AO2 port map( A => temp_10_port, B => n204, C => data(5), D => n205, Z => n193); U72 : AO2 port map( A => temp_0_port, B => n204, C => data(15), D => n205, Z => n203); n206 <= '0'; n207 <= '0'; n208 <= '0'; n209 <= '0'; n210 <= '0'; n211 <= '0'; n212 <= '0'; n213 <= '0'; n214 <= '0'; n215 <= '0'; n216 <= '0'; n217 <= '0'; n218 <= '0'; n219 <= '0'; n220 <= '0'; n222 <= '0'; end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity reg_3 is port( clk, load : in std_logic; data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 15); clear : in std_logic); end reg_3; architecture SYN of reg_3 is component FJK2S port( J, K, CP, CD, TI, TE : in std_logic; Q, QN : out std_logic); end component; component FD1 port( D, CP : in std_logic; Q, QN : out std_logic); end component; component AO7 port( A, B, C : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component AN2 port( A, B : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal temp_2_port, O39_1_port, O39_8_port, temp_6_port, O39_5_port, temp_4_port, temp_9_port, O39_7_port, O39_3_port, temp_0_port, O39_11_port, temp_10_port, temp_14_port, O39_15_port, temp_12_port, O39_13_port, temp_13_port, O39_12_port, temp_15_port, O39_14_port, temp_11_port, O39_10_port, temp_8_port, O39_2_port, temp_1_port, temp_5_port, O39_6_port, O39_4_port, temp_7_port, temp_3_port, O39_0_port , O39_9_port, n239, n240, n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288, n289 : std_logic; begin temp_reg_15_label : FJK2S port map( J => n257, K => n257, CP => clk, CD => n272, TI => data(0), TE => load, Q => temp_15_port, QN => open); temp_reg_14_label : FJK2S port map( J => n258, K => n258, CP => clk, CD => n272, TI => data(1), TE => load, Q => temp_14_port, QN => open); temp_reg_13_label : FJK2S port map( J => n259, K => n259, CP => clk, CD => n272, TI => data(2), TE => load, Q => temp_13_port, QN => open); temp_reg_12_label : FJK2S port map( J => n260, K => n260, CP => clk, CD => n272, TI => data(3), TE => load, Q => temp_12_port, QN => open); temp_reg_11_label : FJK2S port map( J => n261, K => n261, CP => clk, CD => n272, TI => data(4), TE => load, Q => temp_11_port, QN => open); temp_reg_10_label : FJK2S port map( J => n262, K => n262, CP => clk, CD => n272, TI => data(5), TE => load, Q => temp_10_port, QN => open); temp_reg_9_label : FJK2S port map( J => n263, K => n263, CP => clk, CD => n272, TI => data(6), TE => load, Q => temp_9_port, QN => open); temp_reg_8_label : FJK2S port map( J => n264, K => n264, CP => clk, CD => n272, TI => data(7), TE => load, Q => temp_8_port, QN => open); temp_reg_7_label : FJK2S port map( J => n265, K => n265, CP => clk, CD => n272, TI => data(8), TE => load, Q => temp_7_port, QN => open); temp_reg_6_label : FJK2S port map( J => n266, K => n266, CP => clk, CD => n272, TI => data(9), TE => load, Q => temp_6_port, QN => open); temp_reg_5_label : FJK2S port map( J => n267, K => n267, CP => clk, CD => n272, TI => data(10), TE => load, Q => temp_5_port, QN => open); temp_reg_4_label : FJK2S port map( J => n268, K => n268, CP => clk, CD => n272, TI => data(11), TE => load, Q => temp_4_port, QN => open); temp_reg_3_label : FJK2S port map( J => n269, K => n269, CP => clk, CD => n272, TI => data(12), TE => load, Q => temp_3_port, QN => open); temp_reg_2_label : FJK2S port map( J => n270, K => n270, CP => clk, CD => n272, TI => data(13), TE => load, Q => temp_2_port, QN => open); temp_reg_1_label : FJK2S port map( J => n271, K => n271, CP => clk, CD => n272, TI => data(14), TE => load, Q => temp_1_port, QN => open); temp_reg_0_label : FJK2S port map( J => n273, K => n273, CP => clk, CD => n272, TI => data(15), TE => load, Q => temp_0_port, QN => open); O_reg_15_label : FD1 port map( D => O39_15_port, CP => clk, Q => O(0), QN => n274); O_reg_14_label : FD1 port map( D => O39_14_port, CP => clk, Q => O(1), QN => n275); O_reg_13_label : FD1 port map( D => O39_13_port, CP => clk, Q => O(2), QN => n276); O_reg_12_label : FD1 port map( D => O39_12_port, CP => clk, Q => O(3), QN => n277); O_reg_11_label : FD1 port map( D => O39_11_port, CP => clk, Q => O(4), QN => n278); O_reg_10_label : FD1 port map( D => O39_10_port, CP => clk, Q => O(5), QN => n279); O_reg_9_label : FD1 port map( D => O39_9_port, CP => clk, Q => O(6), QN => n280); O_reg_8_label : FD1 port map( D => O39_8_port, CP => clk, Q => O(7), QN => n281); O_reg_7_label : FD1 port map( D => O39_7_port, CP => clk, Q => O(8), QN => n282); O_reg_6_label : FD1 port map( D => O39_6_port, CP => clk, Q => O(9), QN => n283); O_reg_5_label : FD1 port map( D => O39_5_port, CP => clk, Q => O(10), QN => n284); O_reg_4_label : FD1 port map( D => O39_4_port, CP => clk, Q => O(11), QN => n285); O_reg_3_label : FD1 port map( D => O39_3_port, CP => clk, Q => O(12), QN => n286); O_reg_2_label : FD1 port map( D => O39_2_port, CP => clk, Q => O(13), QN => n287); O_reg_1_label : FD1 port map( D => O39_1_port, CP => clk, Q => O(14), QN => n288); O_reg_0_label : FD1 port map( D => O39_0_port, CP => clk, Q => O(15), QN => n289); U38 : AO7 port map( A => n272, B => n274, C => n239, Z => O39_15_port); U39 : AO7 port map( A => n272, B => n275, C => n240, Z => O39_14_port); U40 : AO7 port map( A => n272, B => n276, C => n241, Z => O39_13_port); U41 : AO7 port map( A => n272, B => n277, C => n242, Z => O39_12_port); U42 : AO7 port map( A => n272, B => n278, C => n243, Z => O39_11_port); U43 : AO7 port map( A => n272, B => n279, C => n244, Z => O39_10_port); U44 : AO7 port map( A => n272, B => n280, C => n245, Z => O39_9_port); U45 : AO7 port map( A => n272, B => n281, C => n246, Z => O39_8_port); U46 : AO7 port map( A => n272, B => n282, C => n247, Z => O39_7_port); U47 : AO7 port map( A => n272, B => n283, C => n248, Z => O39_6_port); U48 : AO7 port map( A => n272, B => n284, C => n249, Z => O39_5_port); U49 : AO7 port map( A => n272, B => n285, C => n250, Z => O39_4_port); U50 : AO7 port map( A => n272, B => n286, C => n251, Z => O39_3_port); U51 : AO7 port map( A => n272, B => n287, C => n252, Z => O39_2_port); U52 : AO7 port map( A => n272, B => n288, C => n253, Z => O39_1_port); U53 : AO7 port map( A => n272, B => n289, C => n254, Z => O39_0_port); U54 : IV port map( A => clear, Z => n272); U55 : NR2 port map( A => clear, B => load, Z => n255); U56 : AN2 port map( A => load, B => n272, Z => n256); U57 : AO2 port map( A => temp_9_port, B => n255, C => data(6), D => n256, Z => n245); U58 : AO2 port map( A => temp_8_port, B => n255, C => data(7), D => n256, Z => n246); U59 : AO2 port map( A => temp_7_port, B => n255, C => data(8), D => n256, Z => n247); U60 : AO2 port map( A => temp_6_port, B => n255, C => data(9), D => n256, Z => n248); U61 : AO2 port map( A => temp_5_port, B => n255, C => data(10), D => n256, Z => n249); U62 : AO2 port map( A => temp_4_port, B => n255, C => data(11), D => n256, Z => n250); U63 : AO2 port map( A => temp_3_port, B => n255, C => data(12), D => n256, Z => n251); U64 : AO2 port map( A => temp_2_port, B => n255, C => data(13), D => n256, Z => n252); U65 : AO2 port map( A => temp_1_port, B => n255, C => data(14), D => n256, Z => n253); U66 : AO2 port map( A => temp_15_port, B => n255, C => data(0), D => n256, Z => n239); U67 : AO2 port map( A => temp_14_port, B => n255, C => data(1), D => n256, Z => n240); U68 : AO2 port map( A => temp_13_port, B => n255, C => data(2), D => n256, Z => n241); U69 : AO2 port map( A => temp_12_port, B => n255, C => data(3), D => n256, Z => n242); U70 : AO2 port map( A => temp_11_port, B => n255, C => data(4), D => n256, Z => n243); U71 : AO2 port map( A => temp_10_port, B => n255, C => data(5), D => n256, Z => n244); U72 : AO2 port map( A => temp_0_port, B => n255, C => data(15), D => n256, Z => n254); n257 <= '0'; n258 <= '0'; n259 <= '0'; n260 <= '0'; n261 <= '0'; n262 <= '0'; n263 <= '0'; n264 <= '0'; n265 <= '0'; n266 <= '0'; n267 <= '0'; n268 <= '0'; n269 <= '0'; n270 <= '0'; n271 <= '0'; n273 <= '0'; end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity reg_4 is port( clk, load : in std_logic; data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 15); clear : in std_logic); end reg_4; architecture SYN of reg_4 is component FJK2S port( J, K, CP, CD, TI, TE : in std_logic; Q, QN : out std_logic); end component; component FD1 port( D, CP : in std_logic; Q, QN : out std_logic); end component; component AO7 port( A, B, C : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component AN2 port( A, B : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal temp_2_port, O39_1_port, O39_8_port, temp_6_port, O39_5_port, temp_4_port, temp_9_port, O39_7_port, O39_3_port, temp_0_port, O39_11_port, temp_10_port, temp_14_port, O39_15_port, temp_12_port, O39_13_port, temp_13_port, O39_12_port, temp_15_port, O39_14_port, temp_11_port, O39_10_port, temp_8_port, O39_2_port, temp_1_port, temp_5_port, O39_6_port, O39_4_port, temp_7_port, temp_3_port, O39_0_port , O39_9_port, n325, n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, n373, n374, n375 : std_logic; begin temp_reg_15_label : FJK2S port map( J => n343, K => n343, CP => clk, CD => n358, TI => data(0), TE => load, Q => temp_15_port, QN => open); temp_reg_14_label : FJK2S port map( J => n344, K => n344, CP => clk, CD => n358, TI => data(1), TE => load, Q => temp_14_port, QN => open); temp_reg_13_label : FJK2S port map( J => n345, K => n345, CP => clk, CD => n358, TI => data(2), TE => load, Q => temp_13_port, QN => open); temp_reg_12_label : FJK2S port map( J => n346, K => n346, CP => clk, CD => n358, TI => data(3), TE => load, Q => temp_12_port, QN => open); temp_reg_11_label : FJK2S port map( J => n347, K => n347, CP => clk, CD => n358, TI => data(4), TE => load, Q => temp_11_port, QN => open); temp_reg_10_label : FJK2S port map( J => n348, K => n348, CP => clk, CD => n358, TI => data(5), TE => load, Q => temp_10_port, QN => open); temp_reg_9_label : FJK2S port map( J => n349, K => n349, CP => clk, CD => n358, TI => data(6), TE => load, Q => temp_9_port, QN => open); temp_reg_8_label : FJK2S port map( J => n350, K => n350, CP => clk, CD => n358, TI => data(7), TE => load, Q => temp_8_port, QN => open); temp_reg_7_label : FJK2S port map( J => n351, K => n351, CP => clk, CD => n358, TI => data(8), TE => load, Q => temp_7_port, QN => open); temp_reg_6_label : FJK2S port map( J => n352, K => n352, CP => clk, CD => n358, TI => data(9), TE => load, Q => temp_6_port, QN => open); temp_reg_5_label : FJK2S port map( J => n353, K => n353, CP => clk, CD => n358, TI => data(10), TE => load, Q => temp_5_port, QN => open); temp_reg_4_label : FJK2S port map( J => n354, K => n354, CP => clk, CD => n358, TI => data(11), TE => load, Q => temp_4_port, QN => open); temp_reg_3_label : FJK2S port map( J => n355, K => n355, CP => clk, CD => n358, TI => data(12), TE => load, Q => temp_3_port, QN => open); temp_reg_2_label : FJK2S port map( J => n356, K => n356, CP => clk, CD => n358, TI => data(13), TE => load, Q => temp_2_port, QN => open); temp_reg_1_label : FJK2S port map( J => n357, K => n357, CP => clk, CD => n358, TI => data(14), TE => load, Q => temp_1_port, QN => open); temp_reg_0_label : FJK2S port map( J => n359, K => n359, CP => clk, CD => n358, TI => data(15), TE => load, Q => temp_0_port, QN => open); O_reg_15_label : FD1 port map( D => O39_15_port, CP => clk, Q => O(0), QN => n360); O_reg_14_label : FD1 port map( D => O39_14_port, CP => clk, Q => O(1), QN => n361); O_reg_13_label : FD1 port map( D => O39_13_port, CP => clk, Q => O(2), QN => n362); O_reg_12_label : FD1 port map( D => O39_12_port, CP => clk, Q => O(3), QN => n363); O_reg_11_label : FD1 port map( D => O39_11_port, CP => clk, Q => O(4), QN => n364); O_reg_10_label : FD1 port map( D => O39_10_port, CP => clk, Q => O(5), QN => n365); O_reg_9_label : FD1 port map( D => O39_9_port, CP => clk, Q => O(6), QN => n366); O_reg_8_label : FD1 port map( D => O39_8_port, CP => clk, Q => O(7), QN => n367); O_reg_7_label : FD1 port map( D => O39_7_port, CP => clk, Q => O(8), QN => n368); O_reg_6_label : FD1 port map( D => O39_6_port, CP => clk, Q => O(9), QN => n369); O_reg_5_label : FD1 port map( D => O39_5_port, CP => clk, Q => O(10), QN => n370); O_reg_4_label : FD1 port map( D => O39_4_port, CP => clk, Q => O(11), QN => n371); O_reg_3_label : FD1 port map( D => O39_3_port, CP => clk, Q => O(12), QN => n372); O_reg_2_label : FD1 port map( D => O39_2_port, CP => clk, Q => O(13), QN => n373); O_reg_1_label : FD1 port map( D => O39_1_port, CP => clk, Q => O(14), QN => n374); O_reg_0_label : FD1 port map( D => O39_0_port, CP => clk, Q => O(15), QN => n375); U38 : AO7 port map( A => n358, B => n360, C => n325, Z => O39_15_port); U39 : AO7 port map( A => n358, B => n361, C => n326, Z => O39_14_port); U40 : AO7 port map( A => n358, B => n362, C => n327, Z => O39_13_port); U41 : AO7 port map( A => n358, B => n363, C => n328, Z => O39_12_port); U42 : AO7 port map( A => n358, B => n364, C => n329, Z => O39_11_port); U43 : AO7 port map( A => n358, B => n365, C => n330, Z => O39_10_port); U44 : AO7 port map( A => n358, B => n366, C => n331, Z => O39_9_port); U45 : AO7 port map( A => n358, B => n367, C => n332, Z => O39_8_port); U46 : AO7 port map( A => n358, B => n368, C => n333, Z => O39_7_port); U47 : AO7 port map( A => n358, B => n369, C => n334, Z => O39_6_port); U48 : AO7 port map( A => n358, B => n370, C => n335, Z => O39_5_port); U49 : AO7 port map( A => n358, B => n371, C => n336, Z => O39_4_port); U50 : AO7 port map( A => n358, B => n372, C => n337, Z => O39_3_port); U51 : AO7 port map( A => n358, B => n373, C => n338, Z => O39_2_port); U52 : AO7 port map( A => n358, B => n374, C => n339, Z => O39_1_port); U53 : AO7 port map( A => n358, B => n375, C => n340, Z => O39_0_port); U54 : IV port map( A => clear, Z => n358); U55 : NR2 port map( A => clear, B => load, Z => n341); U56 : AN2 port map( A => load, B => n358, Z => n342); U57 : AO2 port map( A => temp_9_port, B => n341, C => data(6), D => n342, Z => n331); U58 : AO2 port map( A => temp_8_port, B => n341, C => data(7), D => n342, Z => n332); U59 : AO2 port map( A => temp_7_port, B => n341, C => data(8), D => n342, Z => n333); U60 : AO2 port map( A => temp_6_port, B => n341, C => data(9), D => n342, Z => n334); U61 : AO2 port map( A => temp_5_port, B => n341, C => data(10), D => n342, Z => n335); U62 : AO2 port map( A => temp_4_port, B => n341, C => data(11), D => n342, Z => n336); U63 : AO2 port map( A => temp_3_port, B => n341, C => data(12), D => n342, Z => n337); U64 : AO2 port map( A => temp_2_port, B => n341, C => data(13), D => n342, Z => n338); U65 : AO2 port map( A => temp_1_port, B => n341, C => data(14), D => n342, Z => n339); U66 : AO2 port map( A => temp_15_port, B => n341, C => data(0), D => n342, Z => n325); U67 : AO2 port map( A => temp_14_port, B => n341, C => data(1), D => n342, Z => n326); U68 : AO2 port map( A => temp_13_port, B => n341, C => data(2), D => n342, Z => n327); U69 : AO2 port map( A => temp_12_port, B => n341, C => data(3), D => n342, Z => n328); U70 : AO2 port map( A => temp_11_port, B => n341, C => data(4), D => n342, Z => n329); U71 : AO2 port map( A => temp_10_port, B => n341, C => data(5), D => n342, Z => n330); U72 : AO2 port map( A => temp_0_port, B => n341, C => data(15), D => n342, Z => n340); n343 <= '0'; n344 <= '0'; n345 <= '0'; n346 <= '0'; n347 <= '0'; n348 <= '0'; n349 <= '0'; n350 <= '0'; n351 <= '0'; n352 <= '0'; n353 <= '0'; n354 <= '0'; n355 <= '0'; n356 <= '0'; n357 <= '0'; n359 <= '0'; end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity reg_5 is port( clk, load : in std_logic; data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 15); clear : in std_logic); end reg_5; architecture SYN of reg_5 is component FJK2S port( J, K, CP, CD, TI, TE : in std_logic; Q, QN : out std_logic); end component; component FD1 port( D, CP : in std_logic; Q, QN : out std_logic); end component; component AO7 port( A, B, C : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component AN2 port( A, B : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal temp_2_port, O39_1_port, O39_8_port, temp_6_port, O39_5_port, temp_4_port, temp_9_port, O39_7_port, O39_3_port, temp_0_port, O39_11_port, temp_10_port, temp_14_port, O39_15_port, temp_12_port, O39_13_port, temp_13_port, O39_12_port, temp_15_port, O39_14_port, temp_11_port, O39_10_port, temp_8_port, O39_2_port, temp_1_port, temp_5_port, O39_6_port, O39_4_port, temp_7_port, temp_3_port, O39_0_port , O39_9_port, n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, n424, n425, n426 : std_logic; begin temp_reg_15_label : FJK2S port map( J => n394, K => n394, CP => clk, CD => n409, TI => data(0), TE => load, Q => temp_15_port, QN => open); temp_reg_14_label : FJK2S port map( J => n395, K => n395, CP => clk, CD => n409, TI => data(1), TE => load, Q => temp_14_port, QN => open); temp_reg_13_label : FJK2S port map( J => n396, K => n396, CP => clk, CD => n409, TI => data(2), TE => load, Q => temp_13_port, QN => open); temp_reg_12_label : FJK2S port map( J => n397, K => n397, CP => clk, CD => n409, TI => data(3), TE => load, Q => temp_12_port, QN => open); temp_reg_11_label : FJK2S port map( J => n398, K => n398, CP => clk, CD => n409, TI => data(4), TE => load, Q => temp_11_port, QN => open); temp_reg_10_label : FJK2S port map( J => n399, K => n399, CP => clk, CD => n409, TI => data(5), TE => load, Q => temp_10_port, QN => open); temp_reg_9_label : FJK2S port map( J => n400, K => n400, CP => clk, CD => n409, TI => data(6), TE => load, Q => temp_9_port, QN => open); temp_reg_8_label : FJK2S port map( J => n401, K => n401, CP => clk, CD => n409, TI => data(7), TE => load, Q => temp_8_port, QN => open); temp_reg_7_label : FJK2S port map( J => n402, K => n402, CP => clk, CD => n409, TI => data(8), TE => load, Q => temp_7_port, QN => open); temp_reg_6_label : FJK2S port map( J => n403, K => n403, CP => clk, CD => n409, TI => data(9), TE => load, Q => temp_6_port, QN => open); temp_reg_5_label : FJK2S port map( J => n404, K => n404, CP => clk, CD => n409, TI => data(10), TE => load, Q => temp_5_port, QN => open); temp_reg_4_label : FJK2S port map( J => n405, K => n405, CP => clk, CD => n409, TI => data(11), TE => load, Q => temp_4_port, QN => open); temp_reg_3_label : FJK2S port map( J => n406, K => n406, CP => clk, CD => n409, TI => data(12), TE => load, Q => temp_3_port, QN => open); temp_reg_2_label : FJK2S port map( J => n407, K => n407, CP => clk, CD => n409, TI => data(13), TE => load, Q => temp_2_port, QN => open); temp_reg_1_label : FJK2S port map( J => n408, K => n408, CP => clk, CD => n409, TI => data(14), TE => load, Q => temp_1_port, QN => open); temp_reg_0_label : FJK2S port map( J => n410, K => n410, CP => clk, CD => n409, TI => data(15), TE => load, Q => temp_0_port, QN => open); O_reg_15_label : FD1 port map( D => O39_15_port, CP => clk, Q => O(0), QN => n411); O_reg_14_label : FD1 port map( D => O39_14_port, CP => clk, Q => O(1), QN => n412); O_reg_13_label : FD1 port map( D => O39_13_port, CP => clk, Q => O(2), QN => n413); O_reg_12_label : FD1 port map( D => O39_12_port, CP => clk, Q => O(3), QN => n414); O_reg_11_label : FD1 port map( D => O39_11_port, CP => clk, Q => O(4), QN => n415); O_reg_10_label : FD1 port map( D => O39_10_port, CP => clk, Q => O(5), QN => n416); O_reg_9_label : FD1 port map( D => O39_9_port, CP => clk, Q => O(6), QN => n417); O_reg_8_label : FD1 port map( D => O39_8_port, CP => clk, Q => O(7), QN => n418); O_reg_7_label : FD1 port map( D => O39_7_port, CP => clk, Q => O(8), QN => n419); O_reg_6_label : FD1 port map( D => O39_6_port, CP => clk, Q => O(9), QN => n420); O_reg_5_label : FD1 port map( D => O39_5_port, CP => clk, Q => O(10), QN => n421); O_reg_4_label : FD1 port map( D => O39_4_port, CP => clk, Q => O(11), QN => n422); O_reg_3_label : FD1 port map( D => O39_3_port, CP => clk, Q => O(12), QN => n423); O_reg_2_label : FD1 port map( D => O39_2_port, CP => clk, Q => O(13), QN => n424); O_reg_1_label : FD1 port map( D => O39_1_port, CP => clk, Q => O(14), QN => n425); O_reg_0_label : FD1 port map( D => O39_0_port, CP => clk, Q => O(15), QN => n426); U38 : AO7 port map( A => n409, B => n411, C => n376, Z => O39_15_port); U39 : AO7 port map( A => n409, B => n412, C => n377, Z => O39_14_port); U40 : AO7 port map( A => n409, B => n413, C => n378, Z => O39_13_port); U41 : AO7 port map( A => n409, B => n414, C => n379, Z => O39_12_port); U42 : AO7 port map( A => n409, B => n415, C => n380, Z => O39_11_port); U43 : AO7 port map( A => n409, B => n416, C => n381, Z => O39_10_port); U44 : AO7 port map( A => n409, B => n417, C => n382, Z => O39_9_port); U45 : AO7 port map( A => n409, B => n418, C => n383, Z => O39_8_port); U46 : AO7 port map( A => n409, B => n419, C => n384, Z => O39_7_port); U47 : AO7 port map( A => n409, B => n420, C => n385, Z => O39_6_port); U48 : AO7 port map( A => n409, B => n421, C => n386, Z => O39_5_port); U49 : AO7 port map( A => n409, B => n422, C => n387, Z => O39_4_port); U50 : AO7 port map( A => n409, B => n423, C => n388, Z => O39_3_port); U51 : AO7 port map( A => n409, B => n424, C => n389, Z => O39_2_port); U52 : AO7 port map( A => n409, B => n425, C => n390, Z => O39_1_port); U53 : AO7 port map( A => n409, B => n426, C => n391, Z => O39_0_port); U54 : IV port map( A => clear, Z => n409); U55 : NR2 port map( A => clear, B => load, Z => n392); U56 : AN2 port map( A => load, B => n409, Z => n393); U57 : AO2 port map( A => temp_9_port, B => n392, C => data(6), D => n393, Z => n382); U58 : AO2 port map( A => temp_8_port, B => n392, C => data(7), D => n393, Z => n383); U59 : AO2 port map( A => temp_7_port, B => n392, C => data(8), D => n393, Z => n384); U60 : AO2 port map( A => temp_6_port, B => n392, C => data(9), D => n393, Z => n385); U61 : AO2 port map( A => temp_5_port, B => n392, C => data(10), D => n393, Z => n386); U62 : AO2 port map( A => temp_4_port, B => n392, C => data(11), D => n393, Z => n387); U63 : AO2 port map( A => temp_3_port, B => n392, C => data(12), D => n393, Z => n388); U64 : AO2 port map( A => temp_2_port, B => n392, C => data(13), D => n393, Z => n389); U65 : AO2 port map( A => temp_1_port, B => n392, C => data(14), D => n393, Z => n390); U66 : AO2 port map( A => temp_15_port, B => n392, C => data(0), D => n393, Z => n376); U67 : AO2 port map( A => temp_14_port, B => n392, C => data(1), D => n393, Z => n377); U68 : AO2 port map( A => temp_13_port, B => n392, C => data(2), D => n393, Z => n378); U69 : AO2 port map( A => temp_12_port, B => n392, C => data(3), D => n393, Z => n379); U70 : AO2 port map( A => temp_11_port, B => n392, C => data(4), D => n393, Z => n380); U71 : AO2 port map( A => temp_10_port, B => n392, C => data(5), D => n393, Z => n381); U72 : AO2 port map( A => temp_0_port, B => n392, C => data(15), D => n393, Z => n391); n394 <= '0'; n395 <= '0'; n396 <= '0'; n397 <= '0'; n398 <= '0'; n399 <= '0'; n400 <= '0'; n401 <= '0'; n402 <= '0'; n403 <= '0'; n404 <= '0'; n405 <= '0'; n406 <= '0'; n407 <= '0'; n408 <= '0'; n410 <= '0'; end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity reg_6 is port( clk, load : in std_logic; data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 15); clear : in std_logic); end reg_6; architecture SYN of reg_6 is component FJK2S port( J, K, CP, CD, TI, TE : in std_logic; Q, QN : out std_logic); end component; component FD1 port( D, CP : in std_logic; Q, QN : out std_logic); end component; component AO7 port( A, B, C : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component AN2 port( A, B : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal temp_2_port, O39_1_port, O39_8_port, temp_6_port, O39_5_port, temp_4_port, temp_9_port, O39_7_port, O39_3_port, temp_0_port, O39_11_port, temp_10_port, temp_14_port, O39_15_port, temp_12_port, O39_13_port, temp_13_port, O39_12_port, temp_15_port, O39_14_port, temp_11_port, O39_10_port, temp_8_port, O39_2_port, temp_1_port, temp_5_port, O39_6_port, O39_4_port, temp_7_port, temp_3_port, O39_0_port , O39_9_port, n442, n443, n444, n445, n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492 : std_logic; begin temp_reg_15_label : FJK2S port map( J => n460, K => n460, CP => clk, CD => n475, TI => data(0), TE => load, Q => temp_15_port, QN => open); temp_reg_14_label : FJK2S port map( J => n461, K => n461, CP => clk, CD => n475, TI => data(1), TE => load, Q => temp_14_port, QN => open); temp_reg_13_label : FJK2S port map( J => n462, K => n462, CP => clk, CD => n475, TI => data(2), TE => load, Q => temp_13_port, QN => open); temp_reg_12_label : FJK2S port map( J => n463, K => n463, CP => clk, CD => n475, TI => data(3), TE => load, Q => temp_12_port, QN => open); temp_reg_11_label : FJK2S port map( J => n464, K => n464, CP => clk, CD => n475, TI => data(4), TE => load, Q => temp_11_port, QN => open); temp_reg_10_label : FJK2S port map( J => n465, K => n465, CP => clk, CD => n475, TI => data(5), TE => load, Q => temp_10_port, QN => open); temp_reg_9_label : FJK2S port map( J => n466, K => n466, CP => clk, CD => n475, TI => data(6), TE => load, Q => temp_9_port, QN => open); temp_reg_8_label : FJK2S port map( J => n467, K => n467, CP => clk, CD => n475, TI => data(7), TE => load, Q => temp_8_port, QN => open); temp_reg_7_label : FJK2S port map( J => n468, K => n468, CP => clk, CD => n475, TI => data(8), TE => load, Q => temp_7_port, QN => open); temp_reg_6_label : FJK2S port map( J => n469, K => n469, CP => clk, CD => n475, TI => data(9), TE => load, Q => temp_6_port, QN => open); temp_reg_5_label : FJK2S port map( J => n470, K => n470, CP => clk, CD => n475, TI => data(10), TE => load, Q => temp_5_port, QN => open); temp_reg_4_label : FJK2S port map( J => n471, K => n471, CP => clk, CD => n475, TI => data(11), TE => load, Q => temp_4_port, QN => open); temp_reg_3_label : FJK2S port map( J => n472, K => n472, CP => clk, CD => n475, TI => data(12), TE => load, Q => temp_3_port, QN => open); temp_reg_2_label : FJK2S port map( J => n473, K => n473, CP => clk, CD => n475, TI => data(13), TE => load, Q => temp_2_port, QN => open); temp_reg_1_label : FJK2S port map( J => n474, K => n474, CP => clk, CD => n475, TI => data(14), TE => load, Q => temp_1_port, QN => open); temp_reg_0_label : FJK2S port map( J => n476, K => n476, CP => clk, CD => n475, TI => data(15), TE => load, Q => temp_0_port, QN => open); O_reg_15_label : FD1 port map( D => O39_15_port, CP => clk, Q => O(0), QN => n477); O_reg_14_label : FD1 port map( D => O39_14_port, CP => clk, Q => O(1), QN => n478); O_reg_13_label : FD1 port map( D => O39_13_port, CP => clk, Q => O(2), QN => n479); O_reg_12_label : FD1 port map( D => O39_12_port, CP => clk, Q => O(3), QN => n480); O_reg_11_label : FD1 port map( D => O39_11_port, CP => clk, Q => O(4), QN => n481); O_reg_10_label : FD1 port map( D => O39_10_port, CP => clk, Q => O(5), QN => n482); O_reg_9_label : FD1 port map( D => O39_9_port, CP => clk, Q => O(6), QN => n483); O_reg_8_label : FD1 port map( D => O39_8_port, CP => clk, Q => O(7), QN => n484); O_reg_7_label : FD1 port map( D => O39_7_port, CP => clk, Q => O(8), QN => n485); O_reg_6_label : FD1 port map( D => O39_6_port, CP => clk, Q => O(9), QN => n486); O_reg_5_label : FD1 port map( D => O39_5_port, CP => clk, Q => O(10), QN => n487); O_reg_4_label : FD1 port map( D => O39_4_port, CP => clk, Q => O(11), QN => n488); O_reg_3_label : FD1 port map( D => O39_3_port, CP => clk, Q => O(12), QN => n489); O_reg_2_label : FD1 port map( D => O39_2_port, CP => clk, Q => O(13), QN => n490); O_reg_1_label : FD1 port map( D => O39_1_port, CP => clk, Q => O(14), QN => n491); O_reg_0_label : FD1 port map( D => O39_0_port, CP => clk, Q => O(15), QN => n492); U38 : AO7 port map( A => n475, B => n477, C => n442, Z => O39_15_port); U39 : AO7 port map( A => n475, B => n478, C => n443, Z => O39_14_port); U40 : AO7 port map( A => n475, B => n479, C => n444, Z => O39_13_port); U41 : AO7 port map( A => n475, B => n480, C => n445, Z => O39_12_port); U42 : AO7 port map( A => n475, B => n481, C => n446, Z => O39_11_port); U43 : AO7 port map( A => n475, B => n482, C => n447, Z => O39_10_port); U44 : AO7 port map( A => n475, B => n483, C => n448, Z => O39_9_port); U45 : AO7 port map( A => n475, B => n484, C => n449, Z => O39_8_port); U46 : AO7 port map( A => n475, B => n485, C => n450, Z => O39_7_port); U47 : AO7 port map( A => n475, B => n486, C => n451, Z => O39_6_port); U48 : AO7 port map( A => n475, B => n487, C => n452, Z => O39_5_port); U49 : AO7 port map( A => n475, B => n488, C => n453, Z => O39_4_port); U50 : AO7 port map( A => n475, B => n489, C => n454, Z => O39_3_port); U51 : AO7 port map( A => n475, B => n490, C => n455, Z => O39_2_port); U52 : AO7 port map( A => n475, B => n491, C => n456, Z => O39_1_port); U53 : AO7 port map( A => n475, B => n492, C => n457, Z => O39_0_port); U54 : IV port map( A => clear, Z => n475); U55 : NR2 port map( A => clear, B => load, Z => n458); U56 : AN2 port map( A => load, B => n475, Z => n459); U57 : AO2 port map( A => temp_9_port, B => n458, C => data(6), D => n459, Z => n448); U58 : AO2 port map( A => temp_8_port, B => n458, C => data(7), D => n459, Z => n449); U59 : AO2 port map( A => temp_7_port, B => n458, C => data(8), D => n459, Z => n450); U60 : AO2 port map( A => temp_6_port, B => n458, C => data(9), D => n459, Z => n451); U61 : AO2 port map( A => temp_5_port, B => n458, C => data(10), D => n459, Z => n452); U62 : AO2 port map( A => temp_4_port, B => n458, C => data(11), D => n459, Z => n453); U63 : AO2 port map( A => temp_3_port, B => n458, C => data(12), D => n459, Z => n454); U64 : AO2 port map( A => temp_2_port, B => n458, C => data(13), D => n459, Z => n455); U65 : AO2 port map( A => temp_1_port, B => n458, C => data(14), D => n459, Z => n456); U66 : AO2 port map( A => temp_15_port, B => n458, C => data(0), D => n459, Z => n442); U67 : AO2 port map( A => temp_14_port, B => n458, C => data(1), D => n459, Z => n443); U68 : AO2 port map( A => temp_13_port, B => n458, C => data(2), D => n459, Z => n444); U69 : AO2 port map( A => temp_12_port, B => n458, C => data(3), D => n459, Z => n445); U70 : AO2 port map( A => temp_11_port, B => n458, C => data(4), D => n459, Z => n446); U71 : AO2 port map( A => temp_10_port, B => n458, C => data(5), D => n459, Z => n447); U72 : AO2 port map( A => temp_0_port, B => n458, C => data(15), D => n459, Z => n457); n460 <= '0'; n461 <= '0'; n462 <= '0'; n463 <= '0'; n464 <= '0'; n465 <= '0'; n466 <= '0'; n467 <= '0'; n468 <= '0'; n469 <= '0'; n470 <= '0'; n471 <= '0'; n472 <= '0'; n473 <= '0'; n474 <= '0'; n476 <= '0'; end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity reg_7 is port( clk, load : in std_logic; data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 15); clear : in std_logic); end reg_7; architecture SYN of reg_7 is component FJK2S port( J, K, CP, CD, TI, TE : in std_logic; Q, QN : out std_logic); end component; component FD1 port( D, CP : in std_logic; Q, QN : out std_logic); end component; component AO7 port( A, B, C : in std_logic; Z : out std_logic); end component; component IV port( A : in std_logic; Z : out std_logic); end component; component NR2 port( A, B : in std_logic; Z : out std_logic); end component; component AN2 port( A, B : in std_logic; Z : out std_logic); end component; component AO2 port( A, B, C, D : in std_logic; Z : out std_logic); end component; signal temp_2_port, O39_1_port, O39_8_port, temp_6_port, O39_5_port, temp_4_port, temp_9_port, O39_7_port, O39_3_port, temp_0_port, O39_11_port, temp_10_port, temp_14_port, O39_15_port, temp_12_port, O39_13_port, temp_13_port, O39_12_port, temp_15_port, O39_14_port, temp_11_port, O39_10_port, temp_8_port, O39_2_port, temp_1_port, temp_5_port, O39_6_port, O39_4_port, temp_7_port, temp_3_port, O39_0_port , O39_9_port, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, n558, n559, n560 : std_logic; begin temp_reg_15_label : FJK2S port map( J => n528, K => n528, CP => clk, CD => n543, TI => data(0), TE => load, Q => temp_15_port, QN => open); temp_reg_14_label : FJK2S port map( J => n529, K => n529, CP => clk, CD => n543, TI => data(1), TE => load, Q => temp_14_port, QN => open); temp_reg_13_label : FJK2S port map( J => n530, K => n530, CP => clk, CD => n543, TI => data(2), TE => load, Q => temp_13_port, QN => open); temp_reg_12_label : FJK2S port map( J => n531, K => n531, CP => clk, CD => n543, TI => data(3), TE => load, Q => temp_12_port, QN => open); temp_reg_11_label : FJK2S port map( J => n532, K => n532, CP => clk, CD => n543, TI => data(4), TE => load, Q => temp_11_port, QN => open); temp_reg_10_label : FJK2S port map( J => n533, K => n533, CP => clk, CD => n543, TI => data(5), TE => load, Q => temp_10_port, QN => open); temp_reg_9_label : FJK2S port map( J => n534, K => n534, CP => clk, CD => n543, TI => data(6), TE => load, Q => temp_9_port, QN => open); temp_reg_8_label : FJK2S port map( J => n535, K => n535, CP => clk, CD => n543, TI => data(7), TE => load, Q => temp_8_port, QN => open); temp_reg_7_label : FJK2S port map( J => n536, K => n536, CP => clk, CD => n543, TI => data(8), TE => load, Q => temp_7_port, QN => open); temp_reg_6_label : FJK2S port map( J => n537, K => n537, CP => clk, CD => n543, TI => data(9), TE => load, Q => temp_6_port, QN => open); temp_reg_5_label : FJK2S port map( J => n538, K => n538, CP => clk, CD => n543, TI => data(10), TE => load, Q => temp_5_port, QN => open); temp_reg_4_label : FJK2S port map( J => n539, K => n539, CP => clk, CD => n543, TI => data(11), TE => load, Q => temp_4_port, QN => open); temp_reg_3_label : FJK2S port map( J => n540, K => n540, CP => clk, CD => n543, TI => data(12), TE => load, Q => temp_3_port, QN => open); temp_reg_2_label : FJK2S port map( J => n541, K => n541, CP => clk, CD => n543, TI => data(13), TE => load, Q => temp_2_port, QN => open); temp_reg_1_label : FJK2S port map( J => n542, K => n542, CP => clk, CD => n543, TI => data(14), TE => load, Q => temp_1_port, QN => open); temp_reg_0_label : FJK2S port map( J => n544, K => n544, CP => clk, CD => n543, TI => data(15), TE => load, Q => temp_0_port, QN => open); O_reg_15_label : FD1 port map( D => O39_15_port, CP => clk, Q => O(0), QN => n545); O_reg_14_label : FD1 port map( D => O39_14_port, CP => clk, Q => O(1), QN => n546); O_reg_13_label : FD1 port map( D => O39_13_port, CP => clk, Q => O(2), QN => n547); O_reg_12_label : FD1 port map( D => O39_12_port, CP => clk, Q => O(3), QN => n548); O_reg_11_label : FD1 port map( D => O39_11_port, CP => clk, Q => O(4), QN => n549); O_reg_10_label : FD1 port map( D => O39_10_port, CP => clk, Q => O(5), QN => n550); O_reg_9_label : FD1 port map( D => O39_9_port, CP => clk, Q => O(6), QN => n551); O_reg_8_label : FD1 port map( D => O39_8_port, CP => clk, Q => O(7), QN => n552); O_reg_7_label : FD1 port map( D => O39_7_port, CP => clk, Q => O(8), QN => n553); O_reg_6_label : FD1 port map( D => O39_6_port, CP => clk, Q => O(9), QN => n554); O_reg_5_label : FD1 port map( D => O39_5_port, CP => clk, Q => O(10), QN => n555); O_reg_4_label : FD1 port map( D => O39_4_port, CP => clk, Q => O(11), QN => n556); O_reg_3_label : FD1 port map( D => O39_3_port, CP => clk, Q => O(12), QN => n557); O_reg_2_label : FD1 port map( D => O39_2_port, CP => clk, Q => O(13), QN => n558); O_reg_1_label : FD1 port map( D => O39_1_port, CP => clk, Q => O(14), QN => n559); O_reg_0_label : FD1 port map( D => O39_0_port, CP => clk, Q => O(15), QN => n560); U38 : AO7 port map( A => n543, B => n545, C => n510, Z => O39_15_port); U39 : AO7 port map( A => n543, B => n546, C => n511, Z => O39_14_port); U40 : AO7 port map( A => n543, B => n547, C => n512, Z => O39_13_port); U41 : AO7 port map( A => n543, B => n548, C => n513, Z => O39_12_port); U42 : AO7 port map( A => n543, B => n549, C => n514, Z => O39_11_port); U43 : AO7 port map( A => n543, B => n550, C => n515, Z => O39_10_port); U44 : AO7 port map( A => n543, B => n551, C => n516, Z => O39_9_port); U45 : AO7 port map( A => n543, B => n552, C => n517, Z => O39_8_port); U46 : AO7 port map( A => n543, B => n553, C => n518, Z => O39_7_port); U47 : AO7 port map( A => n543, B => n554, C => n519, Z => O39_6_port); U48 : AO7 port map( A => n543, B => n555, C => n520, Z => O39_5_port); U49 : AO7 port map( A => n543, B => n556, C => n521, Z => O39_4_port); U50 : AO7 port map( A => n543, B => n557, C => n522, Z => O39_3_port); U51 : AO7 port map( A => n543, B => n558, C => n523, Z => O39_2_port); U52 : AO7 port map( A => n543, B => n559, C => n524, Z => O39_1_port); U53 : AO7 port map( A => n543, B => n560, C => n525, Z => O39_0_port); U54 : IV port map( A => clear, Z => n543); U55 : NR2 port map( A => clear, B => load, Z => n526); U56 : AN2 port map( A => load, B => n543, Z => n527); U57 : AO2 port map( A => temp_9_port, B => n526, C => data(6), D => n527, Z => n516); U58 : AO2 port map( A => temp_8_port, B => n526, C => data(7), D => n527, Z => n517); U59 : AO2 port map( A => temp_7_port, B => n526, C => data(8), D => n527, Z => n518); U60 : AO2 port map( A => temp_6_port, B => n526, C => data(9), D => n527, Z => n519); U61 : AO2 port map( A => temp_5_port, B => n526, C => data(10), D => n527, Z => n520); U62 : AO2 port map( A => temp_4_port, B => n526, C => data(11), D => n527, Z => n521); U63 : AO2 port map( A => temp_3_port, B => n526, C => data(12), D => n527, Z => n522); U64 : AO2 port map( A => temp_2_port, B => n526, C => data(13), D => n527, Z => n523); U65 : AO2 port map( A => temp_1_port, B => n526, C => data(14), D => n527, Z => n524); U66 : AO2 port map( A => temp_15_port, B => n526, C => data(0), D => n527, Z => n510); U67 : AO2 port map( A => temp_14_port, B => n526, C => data(1), D => n527, Z => n511); U68 : AO2 port map( A => temp_13_port, B => n526, C => data(2), D => n527, Z => n512); U69 : AO2 port map( A => temp_12_port, B => n526, C => data(3), D => n527, Z => n513); U70 : AO2 port map( A => temp_11_port, B => n526, C => data(4), D => n527, Z => n514); U71 : AO2 port map( A => temp_10_port, B => n526, C => data(5), D => n527, Z => n515); U72 : AO2 port map( A => temp_0_port, B => n526, C => data(15), D => n527, Z => n525); n528 <= '0'; n529 <= '0'; n530 <= '0'; n531 <= '0'; n532 <= '0'; n533 <= '0'; n534 <= '0'; n535 <= '0'; n536 <= '0'; n537 <= '0'; n538 <= '0'; n539 <= '0'; n540 <= '0'; n541 <= '0'; n542 <= '0'; n544 <= '0'; end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity tri_state_0 is port( data_in : in std_logic_vector (0 to 15); s : in std_logic; data_out : out std_logic_vector (0 to 15)); end tri_state_0; architecture SYN of tri_state_0 is component BTS4 port( A, E : in std_logic; Z : out std_logic); end component; begin data_out_tri_15_label : BTS4 port map( A => data_in(0), E => s, Z => data_out(0)); data_out_tri_14_label : BTS4 port map( A => data_in(1), E => s, Z => data_out(1)); data_out_tri_13_label : BTS4 port map( A => data_in(2), E => s, Z => data_out(2)); data_out_tri_12_label : BTS4 port map( A => data_in(3), E => s, Z => data_out(3)); data_out_tri_11_label : BTS4 port map( A => data_in(4), E => s, Z => data_out(4)); data_out_tri_10_label : BTS4 port map( A => data_in(5), E => s, Z => data_out(5)); data_out_tri_9_label : BTS4 port map( A => data_in(6), E => s, Z => data_out(6)); data_out_tri_8_label : BTS4 port map( A => data_in(7), E => s, Z => data_out(7)); data_out_tri_7_label : BTS4 port map( A => data_in(8), E => s, Z => data_out(8)); data_out_tri_6_label : BTS4 port map( A => data_in(9), E => s, Z => data_out(9)); data_out_tri_5_label : BTS4 port map( A => data_in(10), E => s, Z => data_out(10)); data_out_tri_4_label : BTS4 port map( A => data_in(11), E => s, Z => data_out(11)); data_out_tri_3_label : BTS4 port map( A => data_in(12), E => s, Z => data_out(12)); data_out_tri_2_label : BTS4 port map( A => data_in(13), E => s, Z => data_out(13)); data_out_tri_1_label : BTS4 port map( A => data_in(14), E => s, Z => data_out(14)); data_out_tri_0_label : BTS4 port map( A => data_in(15), E => s, Z => data_out(15)); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity tri_state_1 is port( data_in : in std_logic_vector (0 to 15); s : in std_logic; data_out : out std_logic_vector (0 to 15)); end tri_state_1; architecture SYN of tri_state_1 is component BTS4 port( A, E : in std_logic; Z : out std_logic); end component; begin data_out_tri_15_label : BTS4 port map( A => data_in(0), E => s, Z => data_out(0)); data_out_tri_14_label : BTS4 port map( A => data_in(1), E => s, Z => data_out(1)); data_out_tri_13_label : BTS4 port map( A => data_in(2), E => s, Z => data_out(2)); data_out_tri_12_label : BTS4 port map( A => data_in(3), E => s, Z => data_out(3)); data_out_tri_11_label : BTS4 port map( A => data_in(4), E => s, Z => data_out(4)); data_out_tri_10_label : BTS4 port map( A => data_in(5), E => s, Z => data_out(5)); data_out_tri_9_label : BTS4 port map( A => data_in(6), E => s, Z => data_out(6)); data_out_tri_8_label : BTS4 port map( A => data_in(7), E => s, Z => data_out(7)); data_out_tri_7_label : BTS4 port map( A => data_in(8), E => s, Z => data_out(8)); data_out_tri_6_label : BTS4 port map( A => data_in(9), E => s, Z => data_out(9)); data_out_tri_5_label : BTS4 port map( A => data_in(10), E => s, Z => data_out(10)); data_out_tri_4_label : BTS4 port map( A => data_in(11), E => s, Z => data_out(11)); data_out_tri_3_label : BTS4 port map( A => data_in(12), E => s, Z => data_out(12)); data_out_tri_2_label : BTS4 port map( A => data_in(13), E => s, Z => data_out(13)); data_out_tri_1_label : BTS4 port map( A => data_in(14), E => s, Z => data_out(14)); data_out_tri_0_label : BTS4 port map( A => data_in(15), E => s, Z => data_out(15)); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity tri_state_2 is port( data_in : in std_logic_vector (0 to 15); s : in std_logic; data_out : out std_logic_vector (0 to 15)); end tri_state_2; architecture SYN of tri_state_2 is component BTS4 port( A, E : in std_logic; Z : out std_logic); end component; begin data_out_tri_15_label : BTS4 port map( A => data_in(0), E => s, Z => data_out(0)); data_out_tri_14_label : BTS4 port map( A => data_in(1), E => s, Z => data_out(1)); data_out_tri_13_label : BTS4 port map( A => data_in(2), E => s, Z => data_out(2)); data_out_tri_12_label : BTS4 port map( A => data_in(3), E => s, Z => data_out(3)); data_out_tri_11_label : BTS4 port map( A => data_in(4), E => s, Z => data_out(4)); data_out_tri_10_label : BTS4 port map( A => data_in(5), E => s, Z => data_out(5)); data_out_tri_9_label : BTS4 port map( A => data_in(6), E => s, Z => data_out(6)); data_out_tri_8_label : BTS4 port map( A => data_in(7), E => s, Z => data_out(7)); data_out_tri_7_label : BTS4 port map( A => data_in(8), E => s, Z => data_out(8)); data_out_tri_6_label : BTS4 port map( A => data_in(9), E => s, Z => data_out(9)); data_out_tri_5_label : BTS4 port map( A => data_in(10), E => s, Z => data_out(10)); data_out_tri_4_label : BTS4 port map( A => data_in(11), E => s, Z => data_out(11)); data_out_tri_3_label : BTS4 port map( A => data_in(12), E => s, Z => data_out(12)); data_out_tri_2_label : BTS4 port map( A => data_in(13), E => s, Z => data_out(13)); data_out_tri_1_label : BTS4 port map( A => data_in(14), E => s, Z => data_out(14)); data_out_tri_0_label : BTS4 port map( A => data_in(15), E => s, Z => data_out(15)); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity tri_state_3 is port( data_in : in std_logic_vector (0 to 15); s : in std_logic; data_out : out std_logic_vector (0 to 15)); end tri_state_3; architecture SYN of tri_state_3 is component BTS4 port( A, E : in std_logic; Z : out std_logic); end component; begin data_out_tri_15_label : BTS4 port map( A => data_in(0), E => s, Z => data_out(0)); data_out_tri_14_label : BTS4 port map( A => data_in(1), E => s, Z => data_out(1)); data_out_tri_13_label : BTS4 port map( A => data_in(2), E => s, Z => data_out(2)); data_out_tri_12_label : BTS4 port map( A => data_in(3), E => s, Z => data_out(3)); data_out_tri_11_label : BTS4 port map( A => data_in(4), E => s, Z => data_out(4)); data_out_tri_10_label : BTS4 port map( A => data_in(5), E => s, Z => data_out(5)); data_out_tri_9_label : BTS4 port map( A => data_in(6), E => s, Z => data_out(6)); data_out_tri_8_label : BTS4 port map( A => data_in(7), E => s, Z => data_out(7)); data_out_tri_7_label : BTS4 port map( A => data_in(8), E => s, Z => data_out(8)); data_out_tri_6_label : BTS4 port map( A => data_in(9), E => s, Z => data_out(9)); data_out_tri_5_label : BTS4 port map( A => data_in(10), E => s, Z => data_out(10)); data_out_tri_4_label : BTS4 port map( A => data_in(11), E => s, Z => data_out(11)); data_out_tri_3_label : BTS4 port map( A => data_in(12), E => s, Z => data_out(12)); data_out_tri_2_label : BTS4 port map( A => data_in(13), E => s, Z => data_out(13)); data_out_tri_1_label : BTS4 port map( A => data_in(14), E => s, Z => data_out(14)); data_out_tri_0_label : BTS4 port map( A => data_in(15), E => s, Z => data_out(15)); end SYN; library IEEE,lsi_10k; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_textio.all; use lsi_10k.COMPONENTS.all; use work.CONV_PACK_LC2_all.all; entity LC2_all is port( rst, clk : in std_logic); end LC2_all; architecture SYN of LC2_all is component register_file port( clk, DR_enable : in std_logic; DR_address, SR1_address, SR2_address : in std_logic_vector (0 to 2); data_in : in std_logic_vector (0 to 15); SR1_out, SR2_out : out std_logic_vector (0 to 15)); end component; component LC2_ALU port( A, B : in std_logic_vector (0 to 15); S : in std_logic_vector (0 to 1); O : out std_logic_vector (0 to 15)); end component; component mem_logic port( read_write : in std_logic; MAR : in std_logic_vector (0 to 15); MIO_enable : in std_logic; mem_enable : out std_logic; mux_sel_out : out std_logic_vector (0 to 1); KBSR_ld, CRTDR_ld, CRTSR_ld : out std_logic); end component; component ram_module port( clk, enable, R_W : in std_logic; addr, data_in : in std_logic_vector (0 to 15); data_out : out std_logic_vector (0 to 15)); end component; component sext port( A : in std_logic_vector (0 to 4); O : out std_logic_vector (0 to 15)); end component; component NZP_logic port( data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 2)); end component; component NZP_reg port( clk, load : in std_logic; data : in std_logic_vector (0 to 2); O : out std_logic_vector (0 to 2); clear : in std_logic); end component; component FSM port( clk, rst : in std_logic; IR : in std_logic_vector (0 to 15); CC : in std_logic_vector (0 to 2); PC_ld : out std_logic; PC_mux : out std_logic_vector (0 to 1); IR_ld : out std_logic; MAR_mux : out std_logic_vector (0 to 1); MAR_gate : out std_logic; DR_addr : out std_logic_vector (0 to 2); DR_enable : out std_logic; SR1_addr, SR2_addr : out std_logic_vector (0 to 2); SR2_mux : out std_logic; ALU_sel : out std_logic_vector (0 to 1); CC_ld, MDR_ld , MAR_ld, PC_gate, ALU_gate, MDR_gate, MDR_mux, MIO_enable, Read_Write, PC_clear, MDR_clear, MAR_clear, IR_clear, CC_clear : out std_logic); end component; component zext8 port( A : in std_logic_vector (0 to 7); O : out std_logic_vector (0 to 15)); end component; component zext10 port( A : in std_logic_vector (0 to 5); O : out std_logic_vector (0 to 15)); end component; component adder port( A, B : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 15)); end component; component cat port( A : in std_logic_vector (0 to 8); B : in std_logic_vector (0 to 6) ; O : out std_logic_vector (0 to 15)); end component; component increment port( data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 15)); end component; component mux2_0 port( a, b : in std_logic_vector (0 to 15); s : in std_logic; mux2output : out std_logic_vector (0 to 15)); end component; component mux2_1 port( a, b : in std_logic_vector (0 to 15); s : in std_logic; mux2output : out std_logic_vector (0 to 15)); end component; component mux4_0 port( c, d, e, f : in std_logic_vector (0 to 15); s : in std_logic_vector (0 to 1); muxoutput : out std_logic_vector (0 to 15)); end component; component mux4_1 port( c, d, e, f : in std_logic_vector (0 to 15); s : in std_logic_vector (0 to 1); muxoutput : out std_logic_vector (0 to 15)); end component; component mux4_2 port( c, d, e, f : in std_logic_vector (0 to 15); s : in std_logic_vector (0 to 1); muxoutput : out std_logic_vector (0 to 15)); end component; component reg_0 port( clk, load : in std_logic; data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 15); clear : in std_logic); end component; component reg_1 port( clk, load : in std_logic; data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 15); clear : in std_logic); end component; component reg_2 port( clk, load : in std_logic; data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 15); clear : in std_logic); end component; component reg_3 port( clk, load : in std_logic; data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 15); clear : in std_logic); end component; component reg_4 port( clk, load : in std_logic; data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 15); clear : in std_logic); end component; component reg_5 port( clk, load : in std_logic; data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 15); clear : in std_logic); end component; component reg_6 port( clk, load : in std_logic; data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 15); clear : in std_logic); end component; component reg_7 port( clk, load : in std_logic; data : in std_logic_vector (0 to 15); O : out std_logic_vector (0 to 15); clear : in std_logic); end component; component tri_state_0 port( data_in : in std_logic_vector (0 to 15); s : in std_logic; data_out : out std_logic_vector (0 to 15)); end component; component tri_state_1 port( data_in : in std_logic_vector (0 to 15); s : in std_logic; data_out : out std_logic_vector (0 to 15)); end component; component tri_state_2 port( data_in : in std_logic_vector (0 to 15); s : in std_logic; data_out : out std_logic_vector (0 to 15)); end component; component tri_state_3 port( data_in : in std_logic_vector (0 to 15); s : in std_logic; data_out : out std_logic_vector (0 to 15)); end component; signal CC_ld, PC_clear, Read_Write, KBSR_ld, ground, MAR_clear, PC_ld, ALU_gate, MAR_gate, CRTSR_ld, MDR_ld, CRTDR_ld, MAR_ld, MDR_mux, MDR_gate , SR2_mux, PC_gate, DR_enable, CC_clear, mem_enable, MDR_clear, MIO_enable, IR_ld, IR_clear, Vcc, sext_out_3_port, SR2_addr_1_port, IR_out_0_port, MAR_mux_out_15_port, data_bus_11_port, SR1_out_8_port, MDR_mux_out_4_port, RAM_out_10_port, zext8_out_5_port, PC_mux_out_8_port, IR_out_1_port, KBDR_out_10_port, MAR_mux_out_13_port, MDR_out_0_port, MAR_out_1_port, PC_out_12_port, sext_out_8_port, zext8_out_15_port, cat_out_1_port, inmux_out_4_port, CRTSR_out_15_port, MDR_out_9_port, increment_out_14_port, SR2_out_8_port, MDR_mux_out_10_port, ALU_out_7_port, MAR_mux_out_6_port, SR2_out_7_port, CRTSR_out_3_port, zext10_out_12_port, MAR_out_8_port, SR1_out_1_port, PC_mux_out_1_port, IR_out_8_port, NZP_out_2_port, sext_out_1_port, cat_out_8_port, IR_out_11_port, RAM_out_5_port, ALU_out_8_port, SR2_addr_0_port, MAR_mux_out_9_port, MDR_out_6_port, cat_out_0_port, ALU_sel_1_port, PC_out_14_port, zext8_out_13_port, inmux_out_2_port, SR1_out_10_port, PC_mux_1_port, MAR_out_7_port, cat_out_7_port, SR1_out_7_port, MDR_mux_out_2_port, IR_out_7_port, zext8_out_3_port, RAM_out_3_port, zext10_out_14_port, sext_out_7_port, PC_mux_out_7_port, MAR_out_0_port, CRTSR_out_13_port, MAR_mux_out_0_port, ALU_out_1_port, SR2_out_1_port, CRTSR_out_5_port, increment_out_12_port, sext_out_9_port, zext8_out_4_port, PC_out_13_port, RAM_out_11_port, data_bus_10_port, CRTSR_out_2_port, inmux_out_5_port, PC_mux_out_9_port, SR1_out_9_port, zext8_out_14_port, MDR_mux_out_5_port, MDR_out_1_port, MAR_mux_out_12_port, ALU_out_6_port, SR2_out_6_port, MAR_mux_out_7_port, increment_out_15_port, CRTSR_out_14_port, MDR_out_8_port, KBDR_out_11_port, SR1_out_15_port, data_bus_2_port, ALU_out_15_port, IR_out_9_port, sext_out_0_port, cat_out_9_port, RAM_out_4_port, MAR_out_9_port, PC_mux_out_0_port, SR1_out_0_port, PC_mux_out_6_port, SR1_out_11_port, inmux_out_3_port, zext10_out_13_port, zext8_out_12_port, MDR_mux_out_11_port, zext8_out_2_port, SR2_out_9_port, MAR_mux_out_8_port , MDR_out_7_port, MAR_mux_out_14_port, ALU_out_9_port, IR_out_10_port, MDR_mux_out_3_port, sext_out_6_port, IR_out_6_port, cat_out_6_port, PC_mux_0_port, MAR_out_6_port, zext10_out_15_port, PC_out_15_port, ALU_sel_0_port, SR1_out_6_port, SR2_mux_out_11_port, KBSR_out_8_port, increment_out_13_port, RAM_out_2_port, CRTSR_out_4_port, SR2_out_0_port, CRTSR_out_12_port, MAR_mux_out_1_port, sext_out_10_port, MAR_out_11_port, ALU_out_0_port, adder_out_1_port, PC_out_4_port, SR1_addr_1_port, SR2_mux_out_5_port, KBDR_out_4_port, PC_mux_out_11_port, data_bus_3_port, KBSR_out_12_port, adder_out_11_port, zext10_out_2_port, KBSR_out_13_port, KBSR_out_1_port, increment_out_3_port, DR_addr_0_port, ALU_out_13_port, increment_out_5_port, KBSR_out_7_port, cat_out_11_port, MDR_out_12_port, adder_out_7_port, PC_out_2_port, adder_out_8_port, SR2_mux_out_3_port, data_bus_5_port, KBSR_out_14_port, KBDR_out_2_port, inmux_out_11_port, SR2_out_11_port, MDR_out_14_port, adder_out_0_port, zext10_out_4_port, MAR_out_10_port, SR2_mux_out_10_port, KBSR_out_9_port, NZP_out_1_port, SR1_addr_0_port, PC_mux_out_10_port, KBDR_out_5_port, SR2_mux_out_4_port, sext_out_11_port, SR2_out_10_port, KBSR_out_15_port, KBDR_out_3_port, DR_addr_1_port, PC_out_5_port, KBSR_out_0_port, zext10_out_3_port, increment_out_2_port, adder_out_10_port, adder_out_9_port, ALU_out_14_port, SR2_mux_out_2_port, PC_out_3_port, MDR_out_13_port, data_bus_4_port, inmux_out_10_port, MDR_out_15_port, adder_out_6_port, cat_out_10_port, CC_out_2_port, zext10_out_5_port, ALU_out_12_port, RAM_out_6_port, KBSR_out_6_port, increment_out_4_port, zext10_out_11_port , MDR_mux_out_13_port, PC_mux_out_2_port, sext_out_2_port, SR2_out_4_port , CRTSR_out_0_port, SR1_out_2_port, MAR_mux_out_5_port, CRTSR_out_9_port, ALU_out_4_port, KBDR_out_13_port, MAR_mux_out_10_port, IR_out_14_port, sext_out_4_port, inmux_out_8_port, zext8_out_6_port, inmux_out_7_port, cat_out_2_port, MAR_out_2_port, MDR_out_3_port, MDR_mux_out_7_port, PC_out_11_port, increment_out_11_port, IR_out_2_port, RAM_out_13_port, data_bus_12_port, KBDR_out_15_port, CRTSR_out_10_port, SR2_out_2_port, ALU_out_2_port, CRTSR_out_6_port, MAR_mux_out_3_port, zext8_out_9_port, cat_out_4_port, IR_out_4_port, zext8_out_0_port, PC_mux_out_4_port, SR1_out_4_port, MDR_mux_out_8_port, MDR_mux_out_15_port, RAM_out_15_port, RAM_out_0_port, data_bus_14_port, MDR_mux_out_1_port, inmux_sel_1_port, inmux_out_1_port, zext8_out_10_port, RAM_out_9_port, MAR_out_4_port, MDR_out_5_port, SR1_out_13_port, SR1_out_3_port, IR_out_12_port, PC_mux_out_3_port, NZP_out_0_port, MAR_mux_out_11_port, MDR_out_2_port, KBDR_out_12_port, MDR_mux_out_12_port, zext10_out_10_port, RAM_out_7_port , SR2_addr_2_port, ALU_out_5_port, MAR_mux_out_4_port, CRTSR_out_1_port, SR2_out_5_port, IR_out_15_port, inmux_out_6_port, SR1_out_14_port, CRTSR_out_8_port, SR2_mux_out_15_port, data_bus_15_port, KBDR_out_14_port , data_bus_13_port, RAM_out_12_port, IR_out_3_port, zext8_out_7_port, PC_out_10_port, MDR_mux_out_6_port, MAR_out_3_port, ALU_out_3_port, MAR_mux_out_2_port, cat_out_3_port, CRTSR_out_7_port, SR2_out_3_port, increment_out_10_port, inmux_out_9_port, SR1_out_5_port, MDR_mux_out_14_port, RAM_out_1_port, CRTSR_out_11_port, MDR_mux_out_9_port, MAR_out_5_port, PC_mux_out_5_port, zext8_out_8_port, cat_out_5_port, sext_out_5_port, inmux_sel_0_port, RAM_out_8_port, RAM_out_14_port, MDR_mux_out_0_port, IR_out_5_port, SR2_out_14_port, MDR_out_4_port, IR_out_13_port, zext8_out_1_port, zext8_out_11_port, SR1_out_12_port, inmux_out_0_port, MDR_out_11_port, cat_out_14_port, increment_out_7_port, KBSR_out_5_port, CC_out_0_port, PC_mux_out_12_port, data_bus_9_port, KBDR_out_7_port, zext10_out_1_port, KBSR_out_2_port, adder_out_12_port, increment_out_0_port, SR2_mux_out_6_port, SR1_addr_2_port, KBSR_out_11_port, SR2_mux_out_12_port, data_bus_0_port, zext10_out_8_port, inmux_out_14_port, MAR_mux_1_port, MAR_out_12_port, PC_out_7_port, increment_out_9_port, sext_out_13_port, adder_out_2_port, sext_out_12_port, data_bus_6_port, SR2_out_12_port, KBDR_out_8_port, zext10_out_7_port, adder_out_14_port, increment_out_6_port, PC_out_8_port , ALU_out_10_port, KBSR_out_4_port, SR2_mux_out_9_port, inmux_out_12_port , cat_out_12_port, adder_out_4_port, PC_out_1_port, MAR_out_14_port, sext_out_15_port, SR2_mux_out_14_port, KBSR_out_3_port, increment_out_1_port, adder_out_13_port, PC_mux_out_14_port, KBDR_out_1_port, SR2_mux_out_0_port, cat_out_15_port, SR2_out_15_port, MDR_out_10_port, zext10_out_0_port, data_bus_8_port, DR_addr_2_port, increment_out_8_port, SR2_mux_out_13_port, PC_out_6_port, zext10_out_9_port, MAR_mux_0_port, data_bus_1_port, SR2_mux_out_8_port, adder_out_3_port, SR2_mux_out_7_port, KBDR_out_6_port, KBSR_out_10_port, PC_mux_out_13_port, inmux_out_15_port, MAR_out_13_port, KBDR_out_9_port, ALU_out_11_port, PC_out_9_port, adder_out_15_port, zext10_out_6_port, CC_out_1_port, SR2_mux_out_1_port, MAR_out_15_port, cat_out_13_port, SR2_out_13_port, adder_out_5_port, inmux_out_13_port, PC_mux_out_15_port, KBDR_out_0_port, data_bus_7_port, sext_out_14_port, PC_out_0_port : std_logic; begin ground <= '0'; U_sext : sext port map( A(0) => IR_out_4_port, A(1) => IR_out_3_port, A(2) => IR_out_2_port, A(3) => IR_out_1_port, A(4) => IR_out_0_port, O(0) => sext_out_15_port, O(1) => sext_out_14_port, O(2) => sext_out_13_port, O(3) => sext_out_12_port, O(4) => sext_out_11_port, O(5) => sext_out_10_port, O(6) => sext_out_9_port, O(7) => sext_out_8_port, O(8) => sext_out_7_port, O(9) => sext_out_6_port, O(10) => sext_out_5_port, O(11) => sext_out_4_port, O(12) => sext_out_3_port, O(13) => sext_out_2_port, O(14) => sext_out_1_port, O(15) => sext_out_0_port); U_zext8 : zext8 port map( A(0) => IR_out_7_port, A(1) => IR_out_6_port, A(2) => IR_out_5_port, A(3) => IR_out_4_port, A(4) => IR_out_3_port, A(5) => IR_out_2_port, A(6) => IR_out_1_port, A(7) => IR_out_0_port, O(0) => open, O(1) => open, O(2) => open, O(3) => open, O(4) => open, O(5) => open, O(6) => open, O(7) => open, O(8) => zext8_out_7_port, O(9) => zext8_out_6_port, O(10) => zext8_out_5_port, O(11) => zext8_out_4_port, O(12) => zext8_out_3_port, O(13) => zext8_out_2_port , O(14) => zext8_out_1_port, O(15) => zext8_out_0_port); Vcc <= '1'; U_ALU_mux : mux2_1 port map( a(0) => SR2_out_15_port, a(1) => SR2_out_14_port, a(2) => SR2_out_13_port, a(3) => SR2_out_12_port, a(4) => SR2_out_11_port, a(5) => SR2_out_10_port, a(6) => SR2_out_9_port, a(7) => SR2_out_8_port, a(8) => SR2_out_7_port, a(9) => SR2_out_6_port, a(10) => SR2_out_5_port, a(11) => SR2_out_4_port, a(12) => SR2_out_3_port, a(13) => SR2_out_2_port, a(14) => SR2_out_1_port, a(15) => SR2_out_0_port, b(0) => sext_out_15_port, b(1) => sext_out_14_port, b(2) => sext_out_13_port, b(3) => sext_out_12_port, b(4) => sext_out_11_port, b(5) => sext_out_10_port, b(6) => sext_out_9_port, b(7) => sext_out_8_port, b(8) => sext_out_7_port, b(9) => sext_out_6_port, b(10) => sext_out_5_port, b(11) => sext_out_4_port, b(12) => sext_out_3_port, b(13) => sext_out_2_port, b(14) => sext_out_1_port, b(15) => sext_out_0_port, s => SR2_mux, mux2output(0) => SR2_mux_out_15_port, mux2output(1) => SR2_mux_out_14_port, mux2output(2) => SR2_mux_out_13_port, mux2output(3) => SR2_mux_out_12_port, mux2output(4) => SR2_mux_out_11_port, mux2output(5) => SR2_mux_out_10_port, mux2output(6) => SR2_mux_out_9_port, mux2output(7) => SR2_mux_out_8_port, mux2output(8) => SR2_mux_out_7_port, mux2output(9) => SR2_mux_out_6_port, mux2output(10) => SR2_mux_out_5_port, mux2output(11) => SR2_mux_out_4_port, mux2output(12) => SR2_mux_out_3_port, mux2output(13) => SR2_mux_out_2_port, mux2output(14) => SR2_mux_out_1_port, mux2output(15) => SR2_mux_out_0_port); U_ALU : LC2_ALU port map( A(0) => SR1_out_15_port, A(1) => SR1_out_14_port, A(2) => SR1_out_13_port, A(3) => SR1_out_12_port, A(4) => SR1_out_11_port, A(5) => SR1_out_10_port, A(6) => SR1_out_9_port, A(7) => SR1_out_8_port, A(8) => SR1_out_7_port, A(9) => SR1_out_6_port, A(10) => SR1_out_5_port, A(11) => SR1_out_4_port, A(12) => SR1_out_3_port, A(13) => SR1_out_2_port, A(14) => SR1_out_1_port, A(15) => SR1_out_0_port, B(0) => SR2_mux_out_15_port, B(1) => SR2_mux_out_14_port, B(2) => SR2_mux_out_13_port, B(3) => SR2_mux_out_12_port, B(4) => SR2_mux_out_11_port, B(5) => SR2_mux_out_10_port, B(6) => SR2_mux_out_9_port, B(7) => SR2_mux_out_8_port, B(8) => SR2_mux_out_7_port, B(9) => SR2_mux_out_6_port, B(10) => SR2_mux_out_5_port, B(11) => SR2_mux_out_4_port, B(12) => SR2_mux_out_3_port, B(13) => SR2_mux_out_2_port, B(14) => SR2_mux_out_1_port, B(15) => SR2_mux_out_0_port, S(0) => ALU_sel_1_port, S(1) => ALU_sel_0_port, O(0) => ALU_out_15_port, O(1) => ALU_out_14_port, O(2) => ALU_out_13_port, O(3) => ALU_out_12_port, O(4) => ALU_out_11_port, O(5) => ALU_out_10_port, O(6) => ALU_out_9_port, O(7) => ALU_out_8_port, O(8) => ALU_out_7_port, O(9) => ALU_out_6_port, O(10) => ALU_out_5_port, O(11) => ALU_out_4_port, O(12) => ALU_out_3_port, O(13) => ALU_out_2_port, O(14) => ALU_out_1_port, O(15) => ALU_out_0_port); U_inmux : mux4_2 port map( c(0) => KBDR_out_15_port, c(1) => KBDR_out_14_port, c(2) => KBDR_out_13_port, c(3) => KBDR_out_12_port, c(4) => KBDR_out_11_port, c(5) => KBDR_out_10_port, c(6) => KBDR_out_9_port, c(7) => KBDR_out_8_port, c(8) => KBDR_out_7_port, c(9) => KBDR_out_6_port, c(10) => KBDR_out_5_port, c(11) => KBDR_out_4_port, c(12) => KBDR_out_3_port, c(13) => KBDR_out_2_port, c(14) => KBDR_out_1_port, c(15) => KBDR_out_0_port, d(0) => KBSR_out_15_port, d(1) => KBSR_out_14_port, d(2) => KBSR_out_13_port, d(3) => KBSR_out_12_port, d(4) => KBSR_out_11_port, d(5) => KBSR_out_10_port, d(6) => KBSR_out_9_port, d(7) => KBSR_out_8_port, d(8) => KBSR_out_7_port, d(9) => KBSR_out_6_port, d(10) => KBSR_out_5_port, d(11) => KBSR_out_4_port, d(12) => KBSR_out_3_port, d(13) => KBSR_out_2_port, d(14) => KBSR_out_1_port, d(15) => KBSR_out_0_port, e(0) => CRTSR_out_15_port, e(1) => CRTSR_out_14_port, e(2) => CRTSR_out_13_port, e(3) => CRTSR_out_12_port, e(4) => CRTSR_out_11_port, e(5) => CRTSR_out_10_port, e(6) => CRTSR_out_9_port, e(7) => CRTSR_out_8_port, e(8) => CRTSR_out_7_port, e(9) => CRTSR_out_6_port, e(10) => CRTSR_out_5_port, e(11) => CRTSR_out_4_port, e(12) => CRTSR_out_3_port , e(13) => CRTSR_out_2_port, e(14) => CRTSR_out_1_port, e(15) => CRTSR_out_0_port, f(0) => RAM_out_15_port, f(1) => RAM_out_14_port, f(2) => RAM_out_13_port, f(3) => RAM_out_12_port, f(4) => RAM_out_11_port, f(5) => RAM_out_10_port, f(6) => RAM_out_9_port, f(7) => RAM_out_8_port, f(8) => RAM_out_7_port, f(9) => RAM_out_6_port, f(10) => RAM_out_5_port, f(11) => RAM_out_4_port, f(12) => RAM_out_3_port, f(13) => RAM_out_2_port, f(14) => RAM_out_1_port, f(15) => RAM_out_0_port, s(0) => inmux_sel_1_port, s(1) => inmux_sel_0_port, muxoutput(0) => inmux_out_15_port, muxoutput(1) => inmux_out_14_port, muxoutput(2) => inmux_out_13_port , muxoutput(3) => inmux_out_12_port, muxoutput(4) => inmux_out_11_port, muxoutput(5) => inmux_out_10_port , muxoutput(6) => inmux_out_9_port, muxoutput(7) => inmux_out_8_port, muxoutput(8) => inmux_out_7_port, muxoutput(9) => inmux_out_6_port, muxoutput(10) => inmux_out_5_port, muxoutput(11) => inmux_out_4_port, muxoutput(12) => inmux_out_3_port, muxoutput(13) => inmux_out_2_port, muxoutput(14) => inmux_out_1_port, muxoutput(15) => inmux_out_0_port); U_IR_reg : reg_7 port map( clk => clk, load => IR_ld, data(0) => data_bus_15_port, data(1) => data_bus_14_port, data(2) => data_bus_13_port, data(3) => data_bus_12_port, data(4) => data_bus_11_port, data(5) => data_bus_10_port, data(6) => data_bus_9_port, data(7) => data_bus_8_port, data(8) => data_bus_7_port, data(9) => data_bus_6_port, data(10) => data_bus_5_port, data(11) => data_bus_4_port, data(12) => data_bus_3_port, data(13) => data_bus_2_port, data(14) => data_bus_1_port, data(15) => data_bus_0_port, O(0) => IR_out_15_port, O(1) => IR_out_14_port, O(2) => IR_out_13_port, O(3) => IR_out_12_port, O(4) => IR_out_11_port, O(5) => IR_out_10_port, O(6) => IR_out_9_port, O(7) => IR_out_8_port, O(8) => IR_out_7_port, O(9) => IR_out_6_port, O(10) => IR_out_5_port, O(11) => IR_out_4_port, O(12) => IR_out_3_port, O(13) => IR_out_2_port, O(14) => IR_out_1_port, O(15) => IR_out_0_port, clear => IR_clear); U_NZP : NZP_logic port map( data(0) => data_bus_15_port, data(1) => data_bus_14_port, data(2) => data_bus_13_port, data(3) => data_bus_12_port, data(4) => data_bus_11_port, data(5) => data_bus_10_port, data(6) => data_bus_9_port, data(7) => data_bus_8_port, data(8) => data_bus_7_port, data(9) => data_bus_6_port, data(10) => data_bus_5_port, data(11) => data_bus_4_port, data(12) => data_bus_3_port, data(13) => data_bus_2_port, data(14) => data_bus_1_port, data(15) => data_bus_0_port, O(0) => NZP_out_2_port, O(1) => NZP_out_1_port, O(2) => NZP_out_0_port); U_NZP_reg : NZP_reg port map( clk => clk, load => CC_ld, data(0) => NZP_out_2_port, data(1) => NZP_out_1_port, data(2) => NZP_out_0_port, O(0) => CC_out_2_port, O(1) => CC_out_1_port, O(2) => CC_out_0_port, clear => CC_clear); U_PC_buff : tri_state_3 port map( data_in(0) => PC_out_15_port, data_in(1) => PC_out_14_port, data_in(2) => PC_out_13_port, data_in(3) => PC_out_12_port, data_in(4) => PC_out_11_port, data_in(5) => PC_out_10_port, data_in(6) => PC_out_9_port, data_in(7) => PC_out_8_port, data_in(8) => PC_out_7_port, data_in(9) => PC_out_6_port, data_in(10) => PC_out_5_port, data_in(11) => PC_out_4_port, data_in(12) => PC_out_3_port, data_in(13) => PC_out_2_port, data_in(14) => PC_out_1_port, data_in(15) => PC_out_0_port, s => PC_gate, data_out(0) => data_bus_15_port, data_out(1) => data_bus_14_port, data_out(2) => data_bus_13_port, data_out(3) => data_bus_12_port, data_out(4) => data_bus_11_port, data_out(5) => data_bus_10_port, data_out(6) => data_bus_9_port, data_out(7) => data_bus_8_port, data_out(8) => data_bus_7_port, data_out(9) => data_bus_6_port, data_out(10) => data_bus_5_port, data_out(11) => data_bus_4_port, data_out(12) => data_bus_3_port, data_out(13) => data_bus_2_port, data_out(14) => data_bus_1_port, data_out(15) => data_bus_0_port); U_CRTSR : reg_6 port map( clk => clk, load => CRTSR_ld, data(0) => MDR_out_15_port, data(1) => MDR_out_14_port, data(2) => MDR_out_13_port, data(3) => MDR_out_12_port, data(4) => MDR_out_11_port, data(5) => MDR_out_10_port, data(6) => MDR_out_9_port, data(7) => MDR_out_8_port, data(8) => MDR_out_7_port, data(9) => MDR_out_6_port, data(10) => MDR_out_5_port, data(11) => MDR_out_4_port, data(12) => MDR_out_3_port, data(13) => MDR_out_2_port, data(14) => MDR_out_1_port, data(15) => MDR_out_0_port, O(0) => CRTSR_out_15_port, O(1) => CRTSR_out_14_port, O(2) => CRTSR_out_13_port, O(3) => CRTSR_out_12_port, O(4) => CRTSR_out_11_port, O(5) => CRTSR_out_10_port, O(6) => CRTSR_out_9_port, O(7) => CRTSR_out_8_port, O(8) => CRTSR_out_7_port, O(9) => CRTSR_out_6_port, O(10) => CRTSR_out_5_port, O(11) => CRTSR_out_4_port, O(12) => CRTSR_out_3_port , O(13) => CRTSR_out_2_port, O(14) => CRTSR_out_1_port, O(15) => CRTSR_out_0_port, clear => ground); U_MDR_mux : mux2_0 port map( a(0) => data_bus_15_port, a(1) => data_bus_14_port, a(2) => data_bus_13_port, a(3) => data_bus_12_port, a(4) => data_bus_11_port, a(5) => data_bus_10_port, a(6) => data_bus_9_port, a(7) => data_bus_8_port, a(8) => data_bus_7_port, a(9) => data_bus_6_port, a(10) => data_bus_5_port, a(11) => data_bus_4_port, a(12) => data_bus_3_port, a(13) => data_bus_2_port, a(14) => data_bus_1_port, a(15) => data_bus_0_port, b(0) => inmux_out_15_port, b(1) => inmux_out_14_port, b(2) => inmux_out_13_port, b(3) => inmux_out_12_port, b(4) => inmux_out_11_port, b(5) => inmux_out_10_port, b(6) => inmux_out_9_port, b(7) => inmux_out_8_port, b(8) => inmux_out_7_port, b(9) => inmux_out_6_port, b(10) => inmux_out_5_port, b(11) => inmux_out_4_port, b(12) => inmux_out_3_port , b(13) => inmux_out_2_port, b(14) => inmux_out_1_port, b(15) => inmux_out_0_port, s => MDR_mux, mux2output(0) => MDR_mux_out_15_port, mux2output(1) => MDR_mux_out_14_port, mux2output(2) => MDR_mux_out_13_port, mux2output(3) => MDR_mux_out_12_port, mux2output(4) => MDR_mux_out_11_port, mux2output(5) => MDR_mux_out_10_port, mux2output(6) => MDR_mux_out_9_port, mux2output(7) => MDR_mux_out_8_port, mux2output(8) => MDR_mux_out_7_port, mux2output(9) => MDR_mux_out_6_port, mux2output(10) => MDR_mux_out_5_port, mux2output(11) => MDR_mux_out_4_port, mux2output(12) => MDR_mux_out_3_port, mux2output(13) => MDR_mux_out_2_port, mux2output(14) => MDR_mux_out_1_port, mux2output(15) => MDR_mux_out_0_port); U_MDR_reg : reg_5 port map( clk => clk, load => MDR_ld, data(0) => MDR_mux_out_15_port, data(1) => MDR_mux_out_14_port, data(2) => MDR_mux_out_13_port, data(3) => MDR_mux_out_12_port, data(4) => MDR_mux_out_11_port, data(5) => MDR_mux_out_10_port, data(6) => MDR_mux_out_9_port, data(7) => MDR_mux_out_8_port, data(8) => MDR_mux_out_7_port, data(9) => MDR_mux_out_6_port, data(10) => MDR_mux_out_5_port, data(11) => MDR_mux_out_4_port, data(12) => MDR_mux_out_3_port, data(13) => MDR_mux_out_2_port, data(14) => MDR_mux_out_1_port, data(15) => MDR_mux_out_0_port, O(0) => MDR_out_15_port, O(1) => MDR_out_14_port, O(2) => MDR_out_13_port, O(3) => MDR_out_12_port, O(4) => MDR_out_11_port, O(5) => MDR_out_10_port, O(6) => MDR_out_9_port, O(7) => MDR_out_8_port, O(8) => MDR_out_7_port, O(9) => MDR_out_6_port, O(10) => MDR_out_5_port, O(11) => MDR_out_4_port, O(12) => MDR_out_3_port, O(13) => MDR_out_2_port, O(14) => MDR_out_1_port, O(15) => MDR_out_0_port, clear => MDR_clear); U_KBDR : reg_4 port map( clk => clk, load => Vcc, data(0) => MDR_out_15_port , data(1) => MDR_out_14_port, data(2) => MDR_out_13_port, data(3) => MDR_out_12_port, data(4) => MDR_out_11_port, data(5) => MDR_out_10_port, data(6) => MDR_out_9_port, data(7) => MDR_out_8_port , data(8) => MDR_out_7_port, data(9) => MDR_out_6_port, data(10) => MDR_out_5_port, data(11) => MDR_out_4_port, data(12) => MDR_out_3_port, data(13) => MDR_out_2_port, data(14) => MDR_out_1_port, data(15) => MDR_out_0_port, O(0) => KBDR_out_15_port, O(1) => KBDR_out_14_port, O(2) => KBDR_out_13_port, O(3) => KBDR_out_12_port, O(4) => KBDR_out_11_port, O(5) => KBDR_out_10_port, O(6) => KBDR_out_9_port, O(7) => KBDR_out_8_port, O(8) => KBDR_out_7_port, O(9) => KBDR_out_6_port, O(10) => KBDR_out_5_port, O(11) => KBDR_out_4_port, O(12) => KBDR_out_3_port, O(13) => KBDR_out_2_port, O(14) => KBDR_out_1_port, O(15) => KBDR_out_0_port, clear => ground); U_MDR_buff : tri_state_2 port map( data_in(0) => MDR_out_15_port, data_in(1) => MDR_out_14_port, data_in(2) => MDR_out_13_port, data_in(3) => MDR_out_12_port, data_in(4) => MDR_out_11_port, data_in(5) => MDR_out_10_port, data_in(6) => MDR_out_9_port, data_in(7) => MDR_out_8_port, data_in(8) => MDR_out_7_port, data_in(9) => MDR_out_6_port, data_in(10) => MDR_out_5_port, data_in(11) => MDR_out_4_port, data_in(12) => MDR_out_3_port, data_in(13) => MDR_out_2_port, data_in(14) => MDR_out_1_port, data_in(15) => MDR_out_0_port, s => MDR_gate, data_out(0) => data_bus_15_port, data_out(1) => data_bus_14_port, data_out(2) => data_bus_13_port, data_out(3) => data_bus_12_port, data_out(4) => data_bus_11_port, data_out(5) => data_bus_10_port, data_out(6) => data_bus_9_port, data_out(7) => data_bus_8_port, data_out(8) => data_bus_7_port, data_out(9) => data_bus_6_port, data_out(10) => data_bus_5_port, data_out(11) => data_bus_4_port, data_out(12) => data_bus_3_port, data_out(13) => data_bus_2_port, data_out(14) => data_bus_1_port, data_out(15) => data_bus_0_port); U_cat : cat port map( A(0) => IR_out_8_port, A(1) => IR_out_7_port, A(2) => IR_out_6_port, A(3) => IR_out_5_port, A(4) => IR_out_4_port, A(5) => IR_out_3_port, A(6) => IR_out_2_port, A(7) => IR_out_1_port, A(8) => IR_out_0_port, B(0) => PC_out_15_port, B(1) => PC_out_14_port, B(2) => PC_out_13_port, B(3) => PC_out_12_port, B(4) => PC_out_11_port, B(5) => PC_out_10_port, B(6) => PC_out_9_port, O(0) => cat_out_15_port, O(1) => cat_out_14_port, O(2) => cat_out_13_port, O(3) => cat_out_12_port, O(4) => cat_out_11_port, O(5) => cat_out_10_port, O(6) => cat_out_9_port, O(7) => cat_out_8_port, O(8) => cat_out_7_port, O(9) => cat_out_6_port, O(10) => cat_out_5_port, O(11) => cat_out_4_port, O(12) => cat_out_3_port, O(13) => cat_out_2_port, O(14) => cat_out_1_port, O(15) => cat_out_0_port); U_reg_bank : register_file port map( clk => clk, DR_enable => DR_enable, DR_address(0) => DR_addr_2_port, DR_address(1) => DR_addr_1_port, DR_address(2) => DR_addr_0_port, SR1_address(0) => SR1_addr_2_port, SR1_address(1) => SR1_addr_1_port, SR1_address(2) => SR1_addr_0_port, SR2_address(0) => SR2_addr_2_port, SR2_address(1) => SR2_addr_1_port, SR2_address(2) => SR2_addr_0_port, data_in(0) => data_bus_15_port, data_in(1) => data_bus_14_port, data_in(2) => data_bus_13_port, data_in(3) => data_bus_12_port, data_in(4) => data_bus_11_port, data_in(5) => data_bus_10_port, data_in(6) => data_bus_9_port, data_in(7) => data_bus_8_port, data_in(8) => data_bus_7_port, data_in(9) => data_bus_6_port, data_in(10) => data_bus_5_port, data_in(11) => data_bus_4_port, data_in(12) => data_bus_3_port, data_in(13) => data_bus_2_port, data_in(14) => data_bus_1_port, data_in(15) => data_bus_0_port, SR1_out(0) => SR1_out_15_port, SR1_out(1) => SR1_out_14_port, SR1_out(2) => SR1_out_13_port, SR1_out(3) => SR1_out_12_port, SR1_out(4) => SR1_out_11_port, SR1_out(5) => SR1_out_10_port, SR1_out(6) => SR1_out_9_port, SR1_out(7) => SR1_out_8_port, SR1_out(8) => SR1_out_7_port, SR1_out(9) => SR1_out_6_port, SR1_out(10) => SR1_out_5_port, SR1_out(11) => SR1_out_4_port, SR1_out(12) => SR1_out_3_port, SR1_out(13) => SR1_out_2_port, SR1_out(14) => SR1_out_1_port, SR1_out(15) => SR1_out_0_port, SR2_out(0) => SR2_out_15_port, SR2_out(1) => SR2_out_14_port, SR2_out(2) => SR2_out_13_port, SR2_out(3) => SR2_out_12_port, SR2_out(4) => SR2_out_11_port, SR2_out(5) => SR2_out_10_port, SR2_out(6) => SR2_out_9_port, SR2_out(7) => SR2_out_8_port, SR2_out(8) => SR2_out_7_port, SR2_out(9) => SR2_out_6_port, SR2_out(10) => SR2_out_5_port, SR2_out(11) => SR2_out_4_port, SR2_out(12) => SR2_out_3_port, SR2_out(13) => SR2_out_2_port, SR2_out(14) => SR2_out_1_port, SR2_out(15) => SR2_out_0_port); U_ALU_buff : tri_state_1 port map( data_in(0) => ALU_out_15_port, data_in(1) => ALU_out_14_port, data_in(2) => ALU_out_13_port, data_in(3) => ALU_out_12_port, data_in(4) => ALU_out_11_port, data_in(5) => ALU_out_10_port, data_in(6) => ALU_out_9_port, data_in(7) => ALU_out_8_port, data_in(8) => ALU_out_7_port, data_in(9) => ALU_out_6_port, data_in(10) => ALU_out_5_port, data_in(11) => ALU_out_4_port, data_in(12) => ALU_out_3_port, data_in(13) => ALU_out_2_port, data_in(14) => ALU_out_1_port, data_in(15) => ALU_out_0_port, s => ALU_gate, data_out(0) => data_bus_15_port, data_out(1) => data_bus_14_port, data_out(2) => data_bus_13_port, data_out(3) => data_bus_12_port, data_out(4) => data_bus_11_port, data_out(5) => data_bus_10_port, data_out(6) => data_bus_9_port, data_out(7) => data_bus_8_port, data_out(8) => data_bus_7_port, data_out(9) => data_bus_6_port, data_out(10) => data_bus_5_port, data_out(11) => data_bus_4_port, data_out(12) => data_bus_3_port, data_out(13) => data_bus_2_port, data_out(14) => data_bus_1_port, data_out(15) => data_bus_0_port); U_ram_logic : mem_logic port map( read_write => Read_Write, MAR(0) => MAR_out_15_port, MAR(1) => MAR_out_14_port, MAR(2) => MAR_out_13_port, MAR(3) => MAR_out_12_port, MAR(4) => MAR_out_11_port, MAR(5) => MAR_out_10_port , MAR(6) => MAR_out_9_port, MAR(7) => MAR_out_8_port , MAR(8) => MAR_out_7_port, MAR(9) => MAR_out_6_port , MAR(10) => MAR_out_5_port, MAR(11) => MAR_out_4_port, MAR(12) => MAR_out_3_port, MAR(13) => MAR_out_2_port, MAR(14) => MAR_out_1_port, MAR(15) => MAR_out_0_port, MIO_enable => MIO_enable, mem_enable => mem_enable, mux_sel_out(0) => inmux_sel_1_port, mux_sel_out(1) => inmux_sel_0_port , KBSR_ld => KBSR_ld, CRTDR_ld => CRTDR_ld, CRTSR_ld => CRTSR_ld); U_zext10 : zext10 port map( A(0) => IR_out_5_port, A(1) => IR_out_4_port, A(2) => IR_out_3_port, A(3) => IR_out_2_port, A(4) => IR_out_1_port, A(5) => IR_out_0_port, O(0) => open, O(1) => open, O(2) => open, O(3) => open, O(4) => open, O(5) => open, O(6) => open, O(7) => open, O(8) => open, O(9) => open, O(10) => zext10_out_5_port, O(11) => zext10_out_4_port, O(12) => zext10_out_3_port, O(13) => zext10_out_2_port, O(14) => zext10_out_1_port, O(15) => zext10_out_0_port); U_ram : ram_module port map( clk => clk, enable => mem_enable, R_W => Read_Write, addr(0) => MAR_out_15_port, addr(1) => MAR_out_14_port, addr(2) => MAR_out_13_port, addr(3) => MAR_out_12_port, addr(4) => MAR_out_11_port, addr(5) => MAR_out_10_port, addr(6) => MAR_out_9_port, addr(7) => MAR_out_8_port, addr(8) => MAR_out_7_port, addr(9) => MAR_out_6_port, addr(10) => MAR_out_5_port, addr(11) => MAR_out_4_port, addr(12) => MAR_out_3_port, addr(13) => MAR_out_2_port, addr(14) => MAR_out_1_port, addr(15) => MAR_out_0_port, data_in(0) => MDR_out_15_port, data_in(1) => MDR_out_14_port, data_in(2) => MDR_out_13_port, data_in(3) => MDR_out_12_port, data_in(4) => MDR_out_11_port, data_in(5) => MDR_out_10_port, data_in(6) => MDR_out_9_port, data_in(7) => MDR_out_8_port, data_in(8) => MDR_out_7_port, data_in(9) => MDR_out_6_port, data_in(10) => MDR_out_5_port, data_in(11) => MDR_out_4_port, data_in(12) => MDR_out_3_port, data_in(13) => MDR_out_2_port, data_in(14) => MDR_out_1_port, data_in(15) => MDR_out_0_port, data_out(0) => RAM_out_15_port, data_out(1) => RAM_out_14_port, data_out(2) => RAM_out_13_port, data_out(3) => RAM_out_12_port, data_out(4) => RAM_out_11_port, data_out(5) => RAM_out_10_port, data_out(6) => RAM_out_9_port, data_out(7) => RAM_out_8_port, data_out(8) => RAM_out_7_port, data_out(9) => RAM_out_6_port, data_out(10) => RAM_out_5_port, data_out(11) => RAM_out_4_port, data_out(12) => RAM_out_3_port, data_out(13) => RAM_out_2_port, data_out(14) => RAM_out_1_port, data_out(15) => RAM_out_0_port); U_MAR_buff : tri_state_0 port map( data_in(0) => MAR_mux_out_15_port, data_in(1) => MAR_mux_out_14_port, data_in(2) => MAR_mux_out_13_port, data_in(3) => MAR_mux_out_12_port, data_in(4) => MAR_mux_out_11_port, data_in(5) => MAR_mux_out_10_port, data_in(6) => MAR_mux_out_9_port, data_in(7) => MAR_mux_out_8_port , data_in(8) => MAR_mux_out_7_port, data_in(9) => MAR_mux_out_6_port, data_in(10) => MAR_mux_out_5_port, data_in(11) => MAR_mux_out_4_port, data_in(12) => MAR_mux_out_3_port, data_in(13) => MAR_mux_out_2_port, data_in(14) => MAR_mux_out_1_port, data_in(15) => MAR_mux_out_0_port, s => MAR_gate, data_out(0) => data_bus_15_port, data_out(1) => data_bus_14_port, data_out(2) => data_bus_13_port, data_out(3) => data_bus_12_port, data_out(4) => data_bus_11_port, data_out(5) => data_bus_10_port, data_out(6) => data_bus_9_port, data_out(7) => data_bus_8_port, data_out(8) => data_bus_7_port, data_out(9) => data_bus_6_port, data_out(10) => data_bus_5_port, data_out(11) => data_bus_4_port, data_out(12) => data_bus_3_port, data_out(13) => data_bus_2_port, data_out(14) => data_bus_1_port, data_out(15) => data_bus_0_port); U_MAR_reg : reg_3 port map( clk => clk, load => MAR_ld, data(0) => data_bus_15_port, data(1) => data_bus_14_port, data(2) => data_bus_13_port, data(3) => data_bus_12_port, data(4) => data_bus_11_port, data(5) => data_bus_10_port, data(6) => data_bus_9_port, data(7) => data_bus_8_port, data(8) => data_bus_7_port, data(9) => data_bus_6_port, data(10) => data_bus_5_port, data(11) => data_bus_4_port, data(12) => data_bus_3_port, data(13) => data_bus_2_port, data(14) => data_bus_1_port, data(15) => data_bus_0_port, O(0) => MAR_out_15_port, O(1) => MAR_out_14_port, O(2) => MAR_out_13_port, O(3) => MAR_out_12_port, O(4) => MAR_out_11_port, O(5) => MAR_out_10_port, O(6) => MAR_out_9_port, O(7) => MAR_out_8_port, O(8) => MAR_out_7_port, O(9) => MAR_out_6_port, O(10) => MAR_out_5_port, O(11) => MAR_out_4_port, O(12) => MAR_out_3_port, O(13) => MAR_out_2_port, O(14) => MAR_out_1_port, O(15) => MAR_out_0_port, clear => MAR_clear); U_adder : adder port map( A(0) => zext10_out_15_port, A(1) => zext10_out_14_port, A(2) => zext10_out_13_port, A(3) => zext10_out_12_port, A(4) => zext10_out_11_port, A(5) => zext10_out_10_port, A(6) => zext10_out_9_port, A(7) => zext10_out_8_port, A(8) => zext10_out_7_port, A(9) => zext10_out_6_port, A(10) => zext10_out_5_port, A(11) => zext10_out_4_port, A(12) => zext10_out_3_port, A(13) => zext10_out_2_port, A(14) => zext10_out_1_port, A(15) => zext10_out_0_port, B(0) => SR1_out_15_port, B(1) => SR1_out_14_port, B(2) => SR1_out_13_port, B(3) => SR1_out_12_port, B(4) => SR1_out_11_port, B(5) => SR1_out_10_port, B(6) => SR1_out_9_port, B(7) => SR1_out_8_port, B(8) => SR1_out_7_port, B(9) => SR1_out_6_port, B(10) => SR1_out_5_port, B(11) => SR1_out_4_port, B(12) => SR1_out_3_port, B(13) => SR1_out_2_port, B(14) => SR1_out_1_port, B(15) => SR1_out_0_port, O(0) => adder_out_15_port, O(1) => adder_out_14_port, O(2) => adder_out_13_port, O(3) => adder_out_12_port, O(4) => adder_out_11_port, O(5) => adder_out_10_port, O(6) => adder_out_9_port, O(7) => adder_out_8_port, O(8) => adder_out_7_port, O(9) => adder_out_6_port, O(10) => adder_out_5_port, O(11) => adder_out_4_port, O(12) => adder_out_3_port , O(13) => adder_out_2_port, O(14) => adder_out_1_port, O(15) => adder_out_0_port); U_MAR_mux : mux4_1 port map( c(0) => cat_out_15_port, c(1) => cat_out_14_port, c(2) => cat_out_13_port, c(3) => cat_out_12_port, c(4) => cat_out_11_port, c(5) => cat_out_10_port, c(6) => cat_out_9_port, c(7) => cat_out_8_port, c(8) => cat_out_7_port, c(9) => cat_out_6_port, c(10) => cat_out_5_port, c(11) => cat_out_4_port, c(12) => cat_out_3_port, c(13) => cat_out_2_port, c(14) => cat_out_1_port, c(15) => cat_out_0_port, d(0) => adder_out_15_port, d(1) => adder_out_14_port, d(2) => adder_out_13_port, d(3) => adder_out_12_port, d(4) => adder_out_11_port, d(5) => adder_out_10_port, d(6) => adder_out_9_port, d(7) => adder_out_8_port, d(8) => adder_out_7_port, d(9) => adder_out_6_port, d(10) => adder_out_5_port, d(11) => adder_out_4_port, d(12) => adder_out_3_port , d(13) => adder_out_2_port, d(14) => adder_out_1_port, d(15) => adder_out_0_port, e(0) => zext8_out_15_port, e(1) => zext8_out_14_port, e(2) => zext8_out_13_port, e(3) => zext8_out_12_port, e(4) => zext8_out_11_port, e(5) => zext8_out_10_port , e(6) => zext8_out_9_port, e(7) => zext8_out_8_port , e(8) => zext8_out_7_port, e(9) => zext8_out_6_port , e(10) => zext8_out_5_port, e(11) => zext8_out_4_port, e(12) => zext8_out_3_port, e(13) => zext8_out_2_port, e(14) => zext8_out_1_port, e(15) => zext8_out_0_port, f(0) => ground, f(1) => ground, f(2) => ground, f(3) => ground, f(4) => ground, f(5) => ground, f(6) => ground, f(7) => ground, f(8) => ground, f(9) => ground, f(10) => ground, f(11) => ground, f(12) => ground, f(13) => ground, f(14) => ground, f(15) => ground, s(0) => MAR_mux_1_port, s(1) => MAR_mux_0_port, muxoutput(0) => MAR_mux_out_15_port, muxoutput(1) => MAR_mux_out_14_port, muxoutput(2) => MAR_mux_out_13_port, muxoutput(3) => MAR_mux_out_12_port, muxoutput(4) => MAR_mux_out_11_port, muxoutput(5) => MAR_mux_out_10_port, muxoutput(6) => MAR_mux_out_9_port, muxoutput(7) => MAR_mux_out_8_port, muxoutput(8) => MAR_mux_out_7_port, muxoutput(9) => MAR_mux_out_6_port, muxoutput(10) => MAR_mux_out_5_port, muxoutput(11) => MAR_mux_out_4_port, muxoutput(12) => MAR_mux_out_3_port, muxoutput(13) => MAR_mux_out_2_port, muxoutput(14) => MAR_mux_out_1_port, muxoutput(15) => MAR_mux_out_0_port); U_PC_mux : mux4_0 port map( c(0) => increment_out_15_port, c(1) => increment_out_14_port, c(2) => increment_out_13_port , c(3) => increment_out_12_port, c(4) => increment_out_11_port, c(5) => increment_out_10_port , c(6) => increment_out_9_port, c(7) => increment_out_8_port, c(8) => increment_out_7_port, c(9) => increment_out_6_port, c(10) => increment_out_5_port, c(11) => increment_out_4_port, c(12) => increment_out_3_port, c(13) => increment_out_2_port, c(14) => increment_out_1_port, c(15) => increment_out_0_port, d(0) => data_bus_15_port, d(1) => data_bus_14_port, d(2) => data_bus_13_port, d(3) => data_bus_12_port, d(4) => data_bus_11_port, d(5) => data_bus_10_port, d(6) => data_bus_9_port, d(7) => data_bus_8_port, d(8) => data_bus_7_port, d(9) => data_bus_6_port, d(10) => data_bus_5_port, d(11) => data_bus_4_port, d(12) => data_bus_3_port, d(13) => data_bus_2_port, d(14) => data_bus_1_port, d(15) => data_bus_0_port, e(0) => SR1_out_15_port, e(1) => SR1_out_14_port, e(2) => SR1_out_13_port, e(3) => SR1_out_12_port, e(4) => SR1_out_11_port, e(5) => SR1_out_10_port, e(6) => SR1_out_9_port, e(7) => SR1_out_8_port, e(8) => SR1_out_7_port, e(9) => SR1_out_6_port, e(10) => SR1_out_5_port, e(11) => SR1_out_4_port, e(12) => SR1_out_3_port, e(13) => SR1_out_2_port, e(14) => SR1_out_1_port, e(15) => SR1_out_0_port, f(0) => cat_out_15_port, f(1) => cat_out_14_port, f(2) => cat_out_13_port, f(3) => cat_out_12_port, f(4) => cat_out_11_port, f(5) => cat_out_10_port, f(6) => cat_out_9_port, f(7) => cat_out_8_port, f(8) => cat_out_7_port, f(9) => cat_out_6_port, f(10) => cat_out_5_port, f(11) => cat_out_4_port, f(12) => cat_out_3_port, f(13) => cat_out_2_port, f(14) => cat_out_1_port, f(15) => cat_out_0_port, s(0) => PC_mux_1_port, s(1) => PC_mux_0_port, muxoutput(0) => PC_mux_out_15_port, muxoutput(1) => PC_mux_out_14_port, muxoutput(2) => PC_mux_out_13_port, muxoutput(3) => PC_mux_out_12_port, muxoutput(4) => PC_mux_out_11_port, muxoutput(5) => PC_mux_out_10_port, muxoutput(6) => PC_mux_out_9_port, muxoutput(7) => PC_mux_out_8_port , muxoutput(8) => PC_mux_out_7_port, muxoutput(9) => PC_mux_out_6_port, muxoutput(10) => PC_mux_out_5_port, muxoutput(11) => PC_mux_out_4_port, muxoutput(12) => PC_mux_out_3_port, muxoutput(13) => PC_mux_out_2_port, muxoutput(14) => PC_mux_out_1_port, muxoutput(15) => PC_mux_out_0_port); U_CRTDR : reg_2 port map( clk => clk, load => CRTDR_ld, data(0) => MDR_out_15_port, data(1) => MDR_out_14_port, data(2) => MDR_out_13_port, data(3) => MDR_out_12_port, data(4) => MDR_out_11_port, data(5) => MDR_out_10_port, data(6) => MDR_out_9_port, data(7) => MDR_out_8_port, data(8) => MDR_out_7_port, data(9) => MDR_out_6_port, data(10) => MDR_out_5_port, data(11) => MDR_out_4_port, data(12) => MDR_out_3_port, data(13) => MDR_out_2_port, data(14) => MDR_out_1_port, data(15) => MDR_out_0_port, O => open, clear => ground); U_ctrl : FSM port map( clk => clk, rst => rst, IR(0) => IR_out_15_port, IR(1) => IR_out_14_port, IR(2) => IR_out_13_port, IR(3) => IR_out_12_port, IR(4) => IR_out_11_port, IR(5) => IR_out_10_port, IR(6) => IR_out_9_port, IR(7) => IR_out_8_port, IR(8) => IR_out_7_port, IR(9) => IR_out_6_port, IR(10) => IR_out_5_port, IR(11) => IR_out_4_port, IR(12) => IR_out_3_port, IR(13) => IR_out_2_port, IR(14) => IR_out_1_port, IR(15) => IR_out_0_port, CC(0) => CC_out_2_port, CC(1) => CC_out_1_port, CC(2) => CC_out_0_port, PC_ld => PC_ld, PC_mux(0) => PC_mux_1_port, PC_mux(1) => PC_mux_0_port, IR_ld => IR_ld, MAR_mux(0) => MAR_mux_1_port, MAR_mux(1) => MAR_mux_0_port, MAR_gate => MAR_gate, DR_addr(0) => DR_addr_2_port, DR_addr(1) => DR_addr_1_port, DR_addr(2) => DR_addr_0_port, DR_enable => DR_enable , SR1_addr(0) => SR1_addr_2_port, SR1_addr(1) => SR1_addr_1_port, SR1_addr(2) => SR1_addr_0_port, SR2_addr(0) => SR2_addr_2_port, SR2_addr(1) => SR2_addr_1_port, SR2_addr(2) => SR2_addr_0_port, SR2_mux => SR2_mux, ALU_sel(0) => ALU_sel_1_port, ALU_sel(1) => ALU_sel_0_port, CC_ld => CC_ld, MDR_ld => MDR_ld, MAR_ld => MAR_ld, PC_gate => PC_gate, ALU_gate => ALU_gate, MDR_gate => MDR_gate, MDR_mux => MDR_mux, MIO_enable => MIO_enable, Read_Write => Read_Write, PC_clear => PC_clear, MDR_clear => MDR_clear, MAR_clear => MAR_clear, IR_clear => IR_clear, CC_clear => open); U_KBSR : reg_1 port map( clk => clk, load => KBSR_ld, data(0) => MDR_out_15_port, data(1) => MDR_out_14_port, data(2) => MDR_out_13_port, data(3) => MDR_out_12_port, data(4) => MDR_out_11_port, data(5) => MDR_out_10_port, data(6) => MDR_out_9_port, data(7) => MDR_out_8_port, data(8) => MDR_out_7_port, data(9) => MDR_out_6_port, data(10) => MDR_out_5_port, data(11) => MDR_out_4_port, data(12) => MDR_out_3_port, data(13) => MDR_out_2_port, data(14) => MDR_out_1_port, data(15) => MDR_out_0_port, O(0) => KBSR_out_15_port, O(1) => KBSR_out_14_port, O(2) => KBSR_out_13_port, O(3) => KBSR_out_12_port, O(4) => KBSR_out_11_port, O(5) => KBSR_out_10_port, O(6) => KBSR_out_9_port, O(7) => KBSR_out_8_port, O(8) => KBSR_out_7_port, O(9) => KBSR_out_6_port, O(10) => KBSR_out_5_port, O(11) => KBSR_out_4_port, O(12) => KBSR_out_3_port, O(13) => KBSR_out_2_port, O(14) => KBSR_out_1_port, O(15) => KBSR_out_0_port, clear => ground); U_increment : increment port map( data(0) => PC_out_15_port, data(1) => PC_out_14_port, data(2) => PC_out_13_port, data(3) => PC_out_12_port, data(4) => PC_out_11_port, data(5) => PC_out_10_port, data(6) => PC_out_9_port, data(7) => PC_out_8_port, data(8) => PC_out_7_port, data(9) => PC_out_6_port, data(10) => PC_out_5_port, data(11) => PC_out_4_port, data(12) => PC_out_3_port , data(13) => PC_out_2_port, data(14) => PC_out_1_port, data(15) => PC_out_0_port, O(0) => increment_out_15_port, O(1) => increment_out_14_port , O(2) => increment_out_13_port, O(3) => increment_out_12_port, O(4) => increment_out_11_port , O(5) => increment_out_10_port, O(6) => increment_out_9_port, O(7) => increment_out_8_port, O(8) => increment_out_7_port, O(9) => increment_out_6_port, O(10) => increment_out_5_port, O(11) => increment_out_4_port, O(12) => increment_out_3_port, O(13) => increment_out_2_port, O(14) => increment_out_1_port, O(15) => increment_out_0_port); U_PC : reg_0 port map( clk => clk, load => PC_ld, data(0) => PC_mux_out_15_port, data(1) => PC_mux_out_14_port, data(2) => PC_mux_out_13_port, data(3) => PC_mux_out_12_port, data(4) => PC_mux_out_11_port, data(5) => PC_mux_out_10_port, data(6) => PC_mux_out_9_port, data(7) => PC_mux_out_8_port, data(8) => PC_mux_out_7_port, data(9) => PC_mux_out_6_port, data(10) => PC_mux_out_5_port, data(11) => PC_mux_out_4_port, data(12) => PC_mux_out_3_port, data(13) => PC_mux_out_2_port, data(14) => PC_mux_out_1_port, data(15) => PC_mux_out_0_port, O(0) => PC_out_15_port, O(1) => PC_out_14_port, O(2) => PC_out_13_port, O(3) => PC_out_12_port, O(4) => PC_out_11_port, O(5) => PC_out_10_port, O(6) => PC_out_9_port, O(7) => PC_out_8_port, O(8) => PC_out_7_port, O(9) => PC_out_6_port, O(10) => PC_out_5_port, O(11) => PC_out_4_port, O(12) => PC_out_3_port, O(13) => PC_out_2_port, O(14) => PC_out_1_port, O(15) => PC_out_0_port, clear => PC_clear); CC_clear <= '0'; zext10_out_6_port <= '0'; zext10_out_7_port <= '0'; zext10_out_8_port <= '0'; zext10_out_9_port <= '0'; zext10_out_10_port <= '0'; zext10_out_11_port <= '0'; zext10_out_12_port <= '0'; zext10_out_13_port <= '0'; zext10_out_14_port <= '0'; zext10_out_15_port <= '0'; zext8_out_8_port <= '0'; zext8_out_9_port <= '0'; zext8_out_10_port <= '0'; zext8_out_11_port <= '0'; zext8_out_12_port <= '0'; zext8_out_13_port <= '0'; zext8_out_14_port <= '0'; zext8_out_15_port <= '0'; end SYN;