Purpose

The purpose of this lab is to download the calculator design of the previous lab onto an FPGA and test it.

Assignment
The topography of the FPGA demoboard and the pin numbers of the input and output switches that you may use is attached.
You can display your result in decimal format using the seven-segment displays on the board(U7, U8). In order to to this you might have to include a binary to seven-segment decoder as another component in your design and let its outputs drive the corresponding LED segment.
The flag register containing bits indicating errors like divide-by-zero, overflow, negative results etc. can be diaplayed on the LEDs D9 through D16.

Conclusion:
You are to demonstrate your implementations to the TA.

This document includes explanation of the following components of the demonstration board.

• J9 Power Jumper
• J12 Unregulated Power Jumper
• Configuration Switches: SW1, SW2, and their schematic
• General Purpose Switch: SW3, and its schematic
• Reset Switch: SW4
• Spare Switch: SW5
• Program Switch: SW6
• 7-segment Digits
• LED Indicators

The Demonstration Board
 

2.    J12     Unregulated Power Input (J12)  The unregulated power input provides a way to power the FPGA Demonstration Board from an unregulated source, such as a 9 V battery or an a.c. adapter. Typically, the input should be 7VDC - 12VDC at 250 mA.  The J12 unregulated power input provides two holes to connect the unregulated power source. The hole with the square pad, marked with a "+" is the positive input. The other hole, marked with a "-" is circuit ground.

3.    SW1    Configuration Switches (SW1).  The following sections describe each of the SW1 switches.

INP  Input Switch (SW1-1)     INP is an extra switch, which is connected to provide an extra logic input to the XC3020A pin 46 and the XC4010E pin 69. The FPGA input pins are set to a logic "1" when the switch is on and a logic "0" when the switch is off. The FPGA pins connected to this switch are intended for use as inputs; however, they have a 1 kilohm resistor that isolates them from the switch, so it is possible to define them as outputs. It is also possible to drive them from an external source by connecting that signal to the FPGA probe point header.

MPE  Multiple Program Enable (SW1-2)     When MPE is on and SPE is off, the configuration PROM (U1) is reset by the RESET pushbutton (SW4). Configuration must be set to the master serial mode. After a Reset or powerup, the first bit stream stored in the serial PROM is loaded into the XC3020A FPGA. IF you press RESET, the serial PROM address pointer is reset. If you press PROG (SW6), the XC3020A is loaded with the first bit stream again. If you press PROG, and do not press RESET, then the XC3020A is loaded with the next bit stream stored in the serial PROM. The number of bit streams that can be sequentially loaded is limited by the size of the serial PROM.

SPE  Single Program Enable (SW1-3)     When SPE is on and MPE is off, the configuration PROM (U1) is reset by the XC3020A's INIT output, which is driven Low whenever you press PROG (SW6). The first bit stream stored in the serial PROM is loaded into the XC3020A FPGA. MPE and SPE must not be on at the same time. MPE and SPE are only used in conjunction with the serial PROMs. The serial PROMs must be configured as OE/ RESET to allow MPE and SPE to function properly.

M0, M1, M2  Mode Pins (SW1-4,5,6)     To configure the XC3020A using the XChecker/Download Cable, these switches must be on, placing the FPGA in slave serial mode. To configure from the onboard serial PROM, these switches must be off to place the FPGA in master serial mode.

MCLK  Master Clock (SW1-7)     When this switch is on, it connects the XC4010E configuration clock (pin 73) to the configuration clock on the XC3020A (pin 60). This connection is used to configure FPGAs in a daisy chain with the XC4010E at the head.

DOUT  Data Out (SW1-8)     When this switch is on, it connects the XC4010E data out line (pin 72) to the data in line of the XC3020A. This connection configures FPGAs in a daisy chain with the XC4010E at the head. MCLK and DOUT should only be used to configure the FPGAs in a daisy chain.

PWR  Power (SW2-1)     Turns the unregulated power input on or off to the +5 V regulator U3.

MPE  Multiple Program Enable (SW2-2)     With MPE turned on and SPE turned off, the configuration PROM (U2) is reset by the RESET pushbutton (SW4). Configuration mode must be set to master-serial. After a Reset or powerup, the first bit stream stored in the serial PROM is loaded into the XC4010E. Pressing RESET resets the serial PROM address pointer. Pressing PROG (SW6) loads the XC4003E with the first bit stream again. If you press PROG without pressing RESET, the XC4010E is loaded with the next bit stream that is stored in the serial PROM. The size of the serial PROM limits the number of bit streams that can be sequentially loaded.

SPE  Single Program Enable (SW2-3)     With SPE turned on and MPE turned off, the configuration PROM (U2) is reset by the XC4010E's INIT output, which is driven Low whenever you press PROG (SW6). The first bit stream stored in the serial PROM is loaded into the XC4010E.
MPE and SPE must not be on at the same time, one must be off when the other  is on. MPE and SPE are only used in conjunction with the serial PROMs. The serial PROMs must be configured as OE/Reset to allow MPE and SPE to function properly.

M0, M1, M2  Mode Pins (SW2-4,5,6)      These three switches must be on to configure the XC4010E using the XChecker/Download Cable. When these switches are on, the FPGA is in slave serial mode. To configure the XC4010E from the onboard serial PROM, these three switches must be off, placing the FPGA in master serial mode.

RST  Reset (SW2-7)     When this switch is on, it connects the RESET pushbutton (SW4).

INIT  Initialize (SW2-8)     When this switch is on, it connects the XC3020A INIT pin to the XC4010E INIT pin. This connection is used to configure FPGAs in a daisy chain with the XC4010E at the head of the chain.
 

 

6.    SW4    RESET Pushbutton (SW4)    Depending on how the Reset signal routing is configured the RESET pushbutton switch can apply an active-Low Reset signal to the FPGAs and configuration PROMs. Reset is normally pulled High through a pull-up resistor.

7.    SW5    SPARE Pushbutton (SW5)    The SPARE pushbutton applies an active-Low signal to the XC3020A on pin 16, and to the XC4010E on pin 18.  The SPARE signal is pulled High through a pull-up resistor.

8.    SW6    PROG Pushbutton (SW6)    The PROG pushbutton applies an active-Low signal to the DONE/PROGRAM input on the XC3020A FPGA socket at pin 45 and to the PROGRAM input on the XC4010E FPGA socket at pin 55. The PROG signal is normally pulled High through a pull-up resistor.

9.    7-Segment Displays (U6, U7, U8)    Three 7-segment displays, are included with the leftmost display (U6) connect to the XC3020A FPGA, and the right two displays (U7 and U8) connect to the XC4010E. Each LED segment is turned on by driving the corresponding FPGA pin 'LOW' with a logic '0.' The decimal point on U8 connects to the INIT pin of the XC4010E (pin 41), and serves as a programming error indicator. The decimal point should be on while the FPGA is in its internal clearing state, then it should remain off during configuration. If the decimal point comes back on, a programming error has occurred.
The decimal points on U6 and U7 are tied to the LDC (Low during configuration) pins of the XC3020A and XC4010E, respectively. The decimal points are on while the FPGAs wait to be configured.

10.    LED Indicators (D1-D8, D9-D16)    Eight LEDs are connected to the I/O pins of each FPGA. D1 through D8 connect to the XC3020A, and D9 through D16 connect to the XC4010E. You can turn on an LED by driving its corresponding FPGA pin Low with a logic "0."