Purpose

The purpose of this lab is to implement a finite state machine in VHDL to perform simple calculations like addition, subtraction, multiplication and division on 2 numbers.

Assignment
The design of the calculator should be divided into 2 parts - a controller and a datapath. The controller is an FSM which issues commands to the datapath based on the current state and the external inputs. This can be a behavioral description. The datapath contains a netlist of functional units like registers, adders, subtractors etc., and hence this design is structural.
The controller basically steps through different states based on the operation specified. When we have finished computing the result, and we go to the final state and assert the data_output line, and reset the FSM back to state 0.
The Datapath does the actual computations. It can have components like a decoder to decode the instruction specified, computation units like adders, subtractors etc, an output register to hold the result when computation is complete. You are free to design in any way that you want but have to keep in mind that it is structural.

Please refer to the figure given below for an example of how the design might be captured. However, your state machine can have a different number of states and different arcs, including loops.

Sample Structure of the Controller and DataPath

Conclusion:
You are to demonstrate your implementations to the TA.

Please include your VHDL source files while turning in the report.