Purpose:

The purpose of this lab is to introduce you to VHDL simulation and synthesis using the ALDEC VHDL simulator and the Xilinx foundation software for synthesis. In this lab, you will implement a behavioral description of a 2-bit counter whose output is fed to a 2-4 decoder. As a result, the top level entity should be structural containg the two components: 2-bit counter and 2-4 decoder.

Description: A behavioral style architecture specifies what a particular system does but provides no information on how the design is implemented.
A testbench would verify that the behaviour of the system is as expected. We then need to translate the design description to another level of abstraction, i.e, from behaviour to structure. This process of translation is called synthesis and can be achieved by using a Synthesis tool like Foundation Express which outputs a netlist. It is similar to the compilation of a high level programming language like C into assembly code.
In this lab, you will specify an entity and test it, synthesize your design using FPGA Express and download it onto an FPGA using the Xilinx Foundation software.

Assignment:

1. Describe a 2-bit counter and a 2-4 decoder in VHDL. Construct a top-level structural entity containing these two components. Write a suitable testbench and simulate it to ensure that it is correct. Information on how to use the ALDEC VHDL simulator ia attached.
2. Synthesize the design using the Xilinx Foundation FPGA software.
3. Import the design into a schematic based system, with I/O pads and nets.
4. Program an FPGA with a design, and perform on-board testing.

Steps to be followed: ALDEC Simulator

Steps to be followed: Xilinx Foundation Software


1. Open the Xilinx Foundation Project Manager: Start ® Programs ® Xilinx Foundation Series ® Xilinx Foundation Project Manager
2. Create a new project within the project manager. Do this by selecting File ® New Project. Enter ``Lab7'' into the Name: field Select ``XC4000E'' from the drop down box in the Family field. Select ``4005EPC84'' from the Part: field. Dlect ``3'' from the drop down box in the Speed: field. Click OK. (Note: The project name should be different from that of your entity or .vhd file)
3. Open ``My Computer `` or ``Windows NT Explorer'' to create a new folder ``express'' in ``C: ® Fndtn ® Active ® Projects ® Lab7. This folder will hold an FPGA Express project.
4. Go back to Project Manager and click HDL Editor. Copy your VHDL program. Limit your entity name and .vhd filename to 5 characters. Save the file (eg. decnt.vhd) in the newly created folder ``express''.
5. Next Open FPGA Express by selecting Start ® Programs ® Xilinx Foundation ® Foundation Express
6. Select the ``Create a new project'' option, and select ``OK''.
7. From the ``Save in'' drop down box, select the newly created express folder. The path is: ``C: ® Fndtn ® Active ® Projects ® Lab7 ® express''. Give the FPGA express project the name ``Express''. Type ``Express'' in the Name field. Select Create.
8. The ``Identify Source files'' dialog box is opened. Select the VHDL files that have been put into the express directory. Select Add.
9. FPGA Express will automatically analyze the file for errors. If there were errors within the file a red `X' will appear over the file icon in the left window. If there were warnings, a red `!' will appear over the icon. If there were no errors or warnings, a green check-mark will appear over the icon. If the file was entered properly, then there should be no warnings or errors. If there were however, this gives us a chance to learn how to debug a file.
   TO DEBUG A FILE:
   To view errors or warnings, select View ® View Errors/Warnings To make corrections to the source code, select the file icon in the left=hand box. It should be highlighted in blue. Do a ``right-click'' with your mouse, and select ``Open Source'' from the menu. Find and fix the errors in the source code. Save the file when ready to re-compile. Return to the FPGA Express window. A red `?' should appear over the file icon. This indicates that the file needs to be reanalyzed by the compiler. To analyze the file, select Synthesis ® Analyze All If the file compiled without errors or warnings, a green ``check-mark'' should be seen. If a `!' or a `X' is seen, keep repeating the above steps until a green check-mark is achieved from the Analysis step.
10. FPGA Express has created an implementation of the chip with the top-level design as its root. The next step is to optimize the design. To do this, on the left half of the window, double click on the fiename, a further level appears. Double click on that. You see the 1st icon gets highlighted (purple, on top of the window), click it. The ``Create ``Implementation'' dialog box should open. Select ``XC4000'' from the Family drop-down box. Select ``XC4005EPC84'' from the Device drop-down box and ``-3'' from the Speed grade drop-down box. Put a mark in the ``Do not insert I/O Pads'' field. Then select ``OK'' You see that a chip appears on the right half of the window under "Chips" and the 2nd icon gets highlighted. Click on it to optimize. You get the Optimized implementation and the 3rd icon gets highlighted. Click it in ``Export Netlist'', click ``Save''. Make sure the path of the .xnf file created is : ``C: ® Fndtn ® Active ® Projects ® Lab7''.
11. Exit the FPGA express environment.
12. Return to the Foundation Project and open the ``Schematic Editor.''
13. Select Hierarchy®Create Macro Symbol from Netlist
14. The ``Import Netlist'' box opens. Select the .XNF file that was generated from your VHDL code. Select Open. Note: If your .XNF file is in the express folder, please copy it to the main project folder, and then import the netlist.
15. Select Mode®Symbols. The Symbols List box opens. Select the entity that you have created. and drag it to the center of your worksheet.
16. Select Mode®Draw Buses. Draw buses on the inputs and outputs of your design which are represented as vectors. At the end of the bus, double click.
17. The ``Add Bus Terminal box'' opens. In the Name field, provide the name of your input/output bus. Use the Up and Down arrows to select the width of the bus. In the I/O marker field, select ``Input'' or ``Output'' respectively for Input bus and Output Bus.
18. Select Bus End.
19. Add IPADs, IBUFs, OPADs, OBUFs to each of the input and outputs as you have done in the previous lab.
20. Draw wires between IPADs and IBUFs and between OPADs and OBUFs.
21. Draw bus taps between the IBUFs and the input bus and between the output bus and the OPADs. To do this Select Mode®Draw Bus Taps. Select on each IBUF/OBUF and you will see a bus tap form to the respective data bus.
22. Name the nets. Change mode to Select and Drag: Mode® Select and Drag. Double click on the net connecting the first OBUF and the bus. Type the label ``O0'' (if your bus is O[3:0]) in the Net Name field. Repeat the steps for all the input and output nets.
23. Lock the nets to pins: Assigns the inputs and outputs to specific parts of the development board. To do this: Change Mode to Select and Drag(Mode®Select and Drag). Double click on the IPAD for I0. The symbol properties dialog box should open. Under the Parameters section, in the Name field, select the LOC option. Under the Description: field, Type P19. Click Add. Double click the ``LOC=P19'' until two black dots appear to the left of it. Click Move. You will be returned to the schematic. Position the empty box to the left of the PAD. When you single click, the following should appear to the left of the PAD: ``LOC=P19.'' Repeat this step with the following pin assignments:

           CLK: P18	This maps to switch SW5(spare) on the board.   
           RESET: P19
           O0: P61
           O1: P62
           O2: P65
           O3: P66
    

24. Save the schematic, and close the Schematic Editor. Select: ``File ® Save'' and ``File ® Exit.''
25. Open the Design manager: ``XACT step'' by double clicking on the ``Implement'' icon.
26. Click ``Yes'' when asked to update the schematic netlist.
27. There should be an open folder icon ``lab7''. Create a new version of the design by selecting Design ® New Version. Select OK. These should be another icon below labeled ver1. Create a new reveision. Select Deisgn ® New Revision. Select Design ® New Revision. The Part field should contain: XC4005E-PC84. The New revision name field should contain rev1. Select OK.
28. Select the newly created icon, and select: Tools ® Flow Engine.
29. The Flow Engine should open. The flow engine will run through four steps: Translate, Map, Place and Route, Configure. The flow engine should run completely without error. You should be returned to the Design Manager. Under ther rev1 icon, it should say ``rev1(Implemented, OK).''
30. Select the rev1 icon. Select Tools ® Hardware Debugger. Click OK when prompted that the Design does not have a READBACK block connected.
31. Select Download ® Download Design. Once downloaded select OK. The demo-board is now programmed and ready to be tested.

Common Problems:
The following have been some of the common problems that many students faced in previous labs, with regard to using the FPGA board and the Xilinx foundation software. Please take care to ensure that you do not commit the same mistakes:

• Do not touch switches SW1 and SW2 on the FPGA board. You have to use only SW3 as your input switches.
• In your VHDL design, limit the entity name to 5 characters.
• The name of your Foundation project should be different from your VHDL file name and the entity that you have created. Failure to do so might give you a ``circular reference error''.
• While drawing your schematic, make sure that the name of the chip you create from the New Symbol Wizard has the same name as your VHDL entity. Also the names of the input and output pins should exactly match the names of the input and output pins in the VHDL entity description. The .XNF file that you import should also have the same name as your entity. Failure to do any of these steps will give you an ``unexpanded error''.
• If you get an ``Input Design empty'' error, it probably means that you haven't imported the right Netlist (.xnf) file into your schematic. To correct the error, go back to Foundation Express, export the netlist into your current project folder and continue. This error may also occur if you don't have the IPAD's, IBUF's, OPAD's or OBUF's connected correctly.

Conclusion: You are to demonstrate your implementations to the TA and submit a lab report with your VHDL code attached.