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WALID A. NAJJAR
Professor
Computer
Science and Engineering
and
Electrical
Engineering
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Copyright Notice
Personal use of the
material in these publications is permitted. However, permission to
reprint/republish this material for advertising or promotional purposes or
for creating new collective works for resale or redistribution to servers
or lists, or to reuse any copyrighted component of this work in other works
must be obtained from the copyright holder (IEEE CS, ACM, Kluwer etc.).
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2008
J. Villarreal
and W. Najjar. Compiled Hardware
Acceleration of Molecular Dynamics Code, in Int. Conf. on Field
Programmable Logic and Applications (FPL’08), Heidelberg, Germany,
September 2008.
A. B.
Buyukkur and W. Najjar. Compiler
Generated Systolic Arrays For Wavefront Algorithm Acceleration on FPGAs,
in Int. Conf. on Field Programmable Logic and Applications (FPL’08),
Heidelberg, Germany, September 2008.
M. Wirthlin, D. Poznanovic, P.
Sundararajan, A. Coppola, D. Pellerin, W. Najjar, R. Bruce, M. Babst, O.
Prichard, P. Palazzari and G. Kuzmanov. OpenFPGA CoreLib Core Library
Interoperability Effort, in Parallel Computing, Vol. 34, No. 4, pp.
231-244, Elsevier.
D. Suresh, B. Agrawal, J. Yang, W.
Najjar. Energy Efficient Encoding Techniques for
Off-Chip Data Busses, to appear in ACM Transactions on Embedded
Computing Systems (TECS), ACM.
Z. Guo, A. B. Buyukkurt, J. Cortes,
A. Mitra, W. Najjar. A Compiler Intermediate
Representation for Reconfigurable Fabrics in International
Journal of Parallel Programming (IJPP), Springer (http://www.springerlink.com/content/u124q758h231414k/).
Z. Guo, W. Najjar, A. B. Buyukkurt.
Efficient Hardware Code Generation
for FPGAs, to appear in
ACM Transactions on Architecture and Compiler Optimizations (TACO), ACM.
2007
A. Mitra, W,
Najjar, L. Bhuyan. Compiling PCRE to
FPGA for Accelerating SNORT IDS, in
the ACM/IEEE Symposium on Architecture for Networking and Communication
Systems (ANCS), Orlando, FL, Dec. 2007.
K. Schleupen, S. Lekuch, R.
Mannion, Z. Guo, W. Najjar and F. Vahid. Dynamic Partial FPGA Reconfiguration
in a Prototype Microprocessor System, in Int. Conf. on Field
Programmable Logic (FPL) Amsterdan, The Netherlands, August 2007.
Jason Villarreal, John Cortes, and
Walid A. Najjar, Compiled Code
Acceleration of NAMD on FPGAs, in
Reconfigurable Systems Summer Institute, Urbana, IL, July 2007.
A. Mitra, Y. Ge and W. Najjar. Performance Analysis of SGI RASC
RC100 Blade on 1D DWT, in Reconfigurable Systems Summer Institute,
Urbana, IL, July 2007.
W. Najjar. Experience with the ROCCC Compiler on RASC, SGI User Group
Conference, Minneapolis, MN, May 2007.
A. Gordon-Ross, P. Vianna, F.
Vahid, W. Najjar and E. Baros. A One-Shot
Configurable-Cache Tuner for Improved Energy and Performance, in
AM/IEEE DATE 2007, Nice, France.
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2006
A. Mitra, Z.
Guo, A. Banerjee, W. Najjar. Dynamic
Co-Processor Architecture for Software Acceleration on CSoCs, IEEE Int.
Conf. on Computer Design (ICCD 2006), San Jose, CA, October 2006.
S. Lin, D. Zeinaliopur-Yazti, V. Kalogeraki, D. Gunopoulos and W. A.
Najjar. Efficient Indexing Data
Structures for Flash-Based Sensor Devices, in ACM Trans. on
Storage Vol.2, No. 4, pp. 468-503, November 2006.
Z. Guo, A. Mitra and W. Najjar. Automation
of IP Core Interface Generation for Reconfigurable Computing, in 16th
International Conference on Field Programmable Logic and Applications (FPL
2006), Madrid, Spain, August 2006.
Z. Guo and W. Najjar. A Compiler
Intermediate Representation for Reconfigurable Fabrics, in 16th
International Conference on Field Programmable Logic and Applications (FPL
2006), Madrid, Spain, August 2006.
D. Kulkarni, W. Najjar, R. Rinker, F. Kurdahi. Compile-time Area Estimation for LUT-based FPGAs.
In ACM Trans. on Design Automation of Electronic Systems, January 2006.
D. Suresh, Z.
Guo, W. Najjar. Automatic compilation framework for Bloom
filter based intrusion detection, Int.
Workshop On Applied Reconfigurable Computing (ARC 2006)
Delft, The
Netherlands, March 1-3, 2006.
B. A.
Buyukkurt, Z. Guo, W. Najjar. Impact
of Loop Unrolling on Throughput, Area and Clock Frequency in ROCCC: C to
VHDL Compiler for FPGAs, Int. Workshop On Applied Reconfigurable
Computing (ARC 2006)
Delft, The Netherlands, March 1-3, 2006.
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2005
D.
Zeinalipour-Yazti, S. Lin, V. Kalogeraki, D. Gunopulos, W. Najjar. MicroHash:
An Efficient Index Structure for Flash-Based Sensor Devices,
in 4th USENIX Conf. on Files and Storage Technologies (FAST 2005), San
Francisco, CA, December 2005.
D. C. Suresh, B. Agrawal, W. A. Najjar, J. Yang. VALVE: Variable
Length Value Encoding for Off-Chip Data Buses,
IEEE Int. Conf. on Computer Design, San Jose, CA, October 2005.
S. Neema, A. Mitra, A. Banerjee, W. Najjar, D. Zeinalipour-Yazti, D.
Gunopulos, V. Kalogeraki. NODES: A
Novel System Design For Embedded Sensor Systems, SPOTS Track, IPSN
2005, Los Angeles, CA.
D. Zeinalipour-Yazti, V. Kalogeraki, D. Gunopulos, A. Mitra, A. Banerjee ,
W. Najjar. Towards
In-Situ Data Storage in Sensor Databases,
PCI 2005, Vollos. Greece.
A. Mitra, A. Banerjee , W. Najjar, D. Zeinalipour-Yazti, D.Gunopulos,
V. Kalogeraki. High Performance, Low Power Sensor Platforms
Featuring Gigabyte Scale Storage, In
Proceedings of Third International Workshop on Measurement, Modeling, and
Performance Analysis of Wireless Sensor Networks (SenMetrics), San Diego,
CA, July 2005.
A.Banerjee, A.Mitra, W.Najjar, D.Zeinalipour-Yazti, V.Kalogeraki and
D.Gunopulos. Co-S:
A High Performance Co-processing Sensor Architecture for Offloading Sensing
and Data Processing, Second
Annual IEEE Communications Society Conference on Sensor and Ad Hoc
Communications and Networks (SECON), Santa Clara, CA, September 2005.
C. Zhang, F. Vahid, J. Yang and W. Najjar. A
Way-Halting Cache for Low-Energy High-Performance Systems.
ACM Trans. on Architecture and Code Optimizations (TACO). Volume 2, No. 1,
March 2005, Pages 34–54.
D.C. Suresh, B. Agrawal, W. A. Najjar and J. Yang, A Tunable Bus Encoder for Off-chip Data
Buses, in International Symposium on Low Power Electronics Design
(ISLPED 2005), San Diego, CA, August 2005.
D.C. Suresh, W. A. Najjar and J. Yang, Power Efficient Instruction Caches for
Embedded Systems, in Embedded Computer Systems: Architectures, MOdeling
and Simulation, (SAMOS V), Samos, Greece, July 2005.
C. Zhang, F. Vahid and W. Najjar. A
highly configurable cache for low energy embedded systems.
ACM Transactions on Embedded Computing Systems. Vol. 4 No. 2. May 2005.
Pages 363-38.
G. Stitt, Z. Guo, F. Vahid, and W. Najjar. Techniques for Synthesizing Binaries
to an Advanced Register/Memory Structure. ACM/SIGDA Symp. on Field
Programmable Gate Arrays (FPGA), Feb. 2005.
D. Zeinalipour-Yazti, S. Neema, D. Gunopulos, V.
Kalogeraki, W. Najjar. Data Acquisition
in Sensor Networks with Large Memories. 1st IEEE International
Workshop on Networking Meets Databases (NetDB), in cooperation with 21st
IEEE Conference on Data Engineering (ICDE 2005) Tokyo, Japan, April
8-9, 2005.
Z. Guo, B. Buyukkurt, W. Najjar and K.
Vissers. Optimized Generation of Data-Path
from C Codes. In ACM/IEEE Design Automation and Test Europe (DATE),
Munich, Germany, March 2005.
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2004
C. Zhang, F.
Vahid, J. Yang, and W. Najjar. A
Way-Halting Cache for Low-Energy High Performance Systems, IEEE Int.
Symp. on Low Power Electronics and Design (ISLPED), Aug 2004.
Z. Guo, A. B. Buyukkurt and W. Najjar. Input Data Reuse In Compiling Window
Operations Onto Reconfigurable Hardware, Proc. ACM Symp. On Languages,
Compilers and Tools for Embedded Systems (LCTES 2004), Washington DC, June
2004.
Z. Guo, W. Najjar, F. Vahid and K. Vissers. A
Quantitative Analysis of the Speedup Factors of FPGAs over Processors, In. Symp. on Field-Programmable
gate Arrays (FPGA), Monterrey, CA, February 2004.
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2003
D. C. Suresh,
J. Yang, C. Zhang, B. Agrawal, W. Najjar. FV-MSB:
A Scheme for Reducing Transition Activity on Data Buses,
Int. Conf. On High Performance Computing, December 2003, Hyderabad, India.
D. C. Suresh, B. Agrawal, J. Yang, W. Najjar, L. Bhuyan. Power
Efficient Encoding Techniques for Off-chip Data Buses, Int.
Conf. on Compilers, Architectures and Synthesis for Embedded Systems
(CASES), October 2003, San Jose, CA.
C. Zhang, F. Vahid, J. Yang and W. Najjar. A
Way-Halting Cache for Low-Energy High-Performance Systems.
IEEE Computer Architecture Letters. Sept. 2003
S. Cotterell, F. Vahid, W. Najjar, H. Hsieh. First
Results with eBlocks: Embedded Systems Building Blocks.
ISSS/CODES 2003, Newport Beach, CA, October 2003.
D. C. Suresh, W. A. Najjar J. Villareal, G. Stitt and F. Vahid. Profiling
Tools for Hardware/Software Partitioning of Embedded Applications.
Proc. ACM Symp. On Languages, Compilers and Tools for Embedded Systems (LCTES
2003), San Diego, CA, June 2003.
C. Zhang, F. Vahid and W. A. Najjar. A Highly Configurable Cache Architecture for
Embedded Systems. Proc. Int. Symp. On
Computer Architecture (ISCA 2003), San Diego, CA, June 2003.
C. Zhang, F. Vahid, W. A. Najjar. Energy Benefits of a Configurable Line Size
Cache for Embedded Systems, Int.
Symposium on VLSI, Feb.2003.
Z. Guo, D. C. Suresh, W. A. Najjar. Programmability and Efficiency in
Reconfigurable Computer Systems,
Workshop on Software Support for Reconfigurable Systems, held in
conjunction with the Int. Conf. Of High-Performance Computer Architecture,
Anaheim, CA, February 2003.
C. Zhang, F. Vahid, J. Yang and W. Najjar. A Way-Halting Cache for Low-Energy
High-Performance Systems. IEEE
Computer Architecture Letters. Sept. 2003.
G. Venkataramani, W. Najjar, F. Kurdahi, N. Bagherzadeh, W. Bohm and J.
Hammes. Automatic Compilation to a Coarse-grained
Reconfigurable System-on-Chip. ACM Trans.
on Embedded Computing Systems, November 2003.
W. Najjar, W. Böhm, B. Draper, J. Hammes, R. Rinker, R. Beveridge, M.
Chawathe and C. Ross. From Algorithms to Hardware – A High-Level
Language Abstraction for Reconfigurable Computing.
IEEE Computer, August 2003.
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2002
D. C. Suresh,
S. Mohanty, W. A. Najjar, L. Bhuyan and F. Vahid. Loop level analysis of security and network
application. Sixth Workshop on Computer
Architecture Evaluation using Commercial Workloads, held in conjunction
with the Int. Conf. Of High-Performance Computer Architecture Anaheim, CA,
February 2003.
D. Kulkarni, W. Najjar, R. Rinker, and F. Kurdahi, Fast Area Estimation to Support Compiler
Optimizations in FPGA-based Reconfigurable Systems,
IEEE Symp. on Field-Programmable Custom Computing Machines (FCCM), Napa,
CA, April 2002.
W. Böhm, R. Beveridge, B. Draper, C. Ross, M. Chawathe, and W. Najjar, Compiling ATR Probing Codes for Execution on
FPGA Hardware. IEEE Symposium on
Field-programmable Custom Computing Machines, Napa Valley, CA, April 21-24,
2002.
J. Villarreal, D. Suresh, G. Stitt, F. Vahid and W. Najjar. Improving Software Performance with
Configurable Logic, Kluwer
Journal on Design Automation of Embedded Systems, November 2002, Vol. 7,
No. 4, pp.325 -339.
W. Böhm, J. Hammes, B. Draper, M. Chawathe, C. Ross, R. Rinker, W. Najjar. Mapping a Single Assignment Programming
Language to Reconfigurable Systems, The
Journal of Supercomputing, Volume 21, pages 117-130, 2002.
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2001
J. Hammes,
A.P.W. Bohm, C. Ross, M. Chawathe, B. Draper and W. Najjar, High Performance Image Processing on FPGAs.
Los Alamos Computer Science Institute Symposium, Santa Fe, NM, Oct. 15-18,
2001.
B. Draper, W. Bohm, J. Hammes, W. Najjar, R. Beveridge, C. Ross, M.
Chawathe, M. Desai, J. Bins, Compiling SA-C Programs to FPGAs: Performance
Results, Int. Conf. on Vision Systems,
Vancouver, July 7-8, 2001. p. 220-235.
G. Venkataramani, W. Najjar, F. Kurdahi, N. Bagherzadeh, W. Bohm. A Compiler Framework for Mapping
Applications to a Coarse-grained Reconfigurable Computer Architecture,
in Int. Conf. on Compiler, Architecture and Synthesis for Embedded Systems
(CASES 2001), Atlanta, GA, November 2001.
A.P.W. Böhm, B. Draper, W. Najjar, J. Hammes, R. Rinker, M. Chawathe,
C. Ross. One-Step Compilation of Image Processing
Algorithms to FPGAs, in IEEE
Symposium on Field-Configurable Custom Machines (FCCM 2001). Rohnert Park,
CA, April 30 - May 2, 2001.
J. Hammes, A.P.W. Böhm, C. Ross, M. Chawathe, B. Draper, R. Rinker, W. Najjar.
Loop Fusion and Temporal Common Subexpression
Elimination in Window-based Loops, in
Reconfigurable Architectures Workshop (RAW'01) held in conjunction with the
Int. Parallel and Distributed
Processing Symp. (IPDPS'01). San Francisco, CA, April 27, 2001.
D. Kumar, W. Najjar and P. K. Srimani. Performance Evaluation of a New Hardware
Supported Multicast Scheme for K-ary N-cubes,
in Workshop on Communication
Architectures for Clusters (CAC'01) held in conjunction with the Int. Parallel and Distributed Processing
Symp. (IPDPS'01). San Francisco, CA, April 27, 2001.
D. Kumar, W. Najjar and P. K. Srimani. A New Adaptive Hardware Tree-Based Multicast
Routing in K-Ary N-Cubes, in IEEE
Trans. on Computers, Vol. 50(7), July 2001.
R. Rinker, M. Carter, A. Patel, M. Chawathe, C. Ross, J. Hammes, W. Najjar
and A.P.W. Böhm. An Automated Process for Compiling Dataflow
Graphs into Hardware. IEEE Trans.
on VLSI, Vol 9(1), February 2001.
L. Roh, B. Shankar, W. Bohm, and W. Najjar. Resource
Management in Dataflow-Based Multithreaded Execution, in Journal of
Parallel and Distributed Computing 61, 581608 ( 2001 ), pages 581-608.
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1995
to 2000
B. Draper, W.
Najjar, W. Böhm, J. Hammes, R. Rinker, C. Ross, M. Chawathe, J. Bins. Compiling and Optimizing Image Processing
Algorithms for FPGA's, in Int.
Workshop on Computer Architecture for Machine Performance. Padova,
Italy, September 11-13 2000.
R. Rinker, J. Hammes, W. A. Najjar, W. Böhm, B. Draper. Compiling Image Processing Applications to
Reconfigurable Hardware, in IEEE
International Conference on Application-specific Systems, Architectures and
Processors, Boston, MA, July 10-12 2000.
J. Hammes, R. Rinker, W. Böhm, W. A. Najjar, Bruce
Draper, A High Level, Algorithmic
Programming Language and Compiler for Reconfigurable Systems, in 2nd
Workshop on the Engineering of
Reconfigurable Hardware/Software Objects (ENREGLE), part of the Int.
Conf. on Parallel and Distributed Processing Techniques and Applications
(PDPTA'2000), Las Vegas, NV, June 26-29 2000.
J. Hammes, R. Rinker, W. Böhm, W. Najjar, B. Draper, and
R. Beveridge Cameron: High Level
Language Compilation for Reconfigurable Systems. Conference on Parallel Architectures and Compilation Techniques,
Newport Beach, CA, Oct. 12-16 1999.
J. Hammes, R. Rinker, W. Böhm, W. Najjar. Compiling a High--level Language to
Reconfigurable Systems. Compiler
and Architecture Support for Embedded Systems (CASES'99), Washington
DC, Oct. 1999.
J. Bins, B.A. Draper, W.A.P. Böhm and W. Najjar. Precision vs. Error in JPEG Compression.
Parallel and Distributed Methods for Image
Processing III, Denver, CO, July 22, 1999.
D. Miller and W. Najjar. Combining adaptive and deterministic
routing: Evaluation of a hybrid router.
In 3rd Workshop on Communication, Architecture, and Applications for
Network-based Parallel Computing (CANPC'99), Orlando, FA, January 1999.
W. Najjar, E. Lee and G. Gao, Advances in the dataflow computational
model, Parallel Computing, North-Holland, Vol. 25, No. 13-14, pages
1907-1929, December 1999 (invited paper).
W. Najjar, B. Draper, A.P.W. Böhm, R. Beveridge. The Cameron Project: High-Level
Programming of Image Processing Applications on Reconfigurable Computing
Machines. In PACT’98 – Workshop
on Reconfigurable Computing. Paris, FRANCE, October 1998.
D. Miller and W. Najjar. Empirical Evaluation of Deterministic and
Adaptive Routing with Constant-Area Routers. In Proc. Int. Conf. on Parallel Architectures and Compilation
Techniques (PACT'97), San Francisco, November 1997.
J-L. Gaudiot, W. Böhm, W. Najjar, T. DeBoni, J. Feo, and
P. Miller. The Sisal model of functional
programming and its implementation. In 2nd Aizu Int. Conf. on Parallel Architectures/Algorithm Synthesis,
Aizu, Japan, March 1997.
J-L. Gaudiot, W. Böhm, T. DeBoni, J. Feo, P. Miller and
W. Najjar. The Sisal
Project: Real World Functional Programming; in Languages, Compilation
Techniques and Run Time Systems for Scalable Parallel Systems, Recent
Advances and Future Perspectives, Springer Verlag,Lecture Notes in Computer
Science Series,1997.
D. Miller and W. Najjar. Preliminary Evaluation of a Hybrid
Deterministic/Adaptive Router. In Proc.
Parallel Computing, Routing and Communication Workshop (PCRCW'97),
Atlanta, June 1997.
M. Annavaram and W. Najjar. Comparison of two storage models in
data-driven multithreaded architectures. In Proc. Eight IEEE Symp. on Parallel and Distributed Processing,
New Orleans, LA, October 1996.
A. Lagman and W. Najjar. Analysis of buffer design for adaptive
routing in direct networks. In Int.
Workshop on Modeling, Analysis and Simulation of Computer and
Telecommunication Systems (MASCOT'96), February 1996.
L. Roh and W. Najjar.
Design of storage hierarchy in multithreaded architectures. In IEEE/ACM Int. Symp. on Microarchitecture
(MICRO-28), November 1995.
L. Roh and W. Najjar. Analysis of communication and overhead
reduction in multithreaded execution. In Int. Conf. on Parallel Architectures and Compilation Techniques,
pages 122-130, June 1995.
B. Shankar, L. Roh, W. Böhm, and W. Najjar. Control of loop parallelism in
multithreaded code. In Int. Conf.
on Parallel Architectures and Compilation Techniques, pages 131-139,
June 1995.
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