Project Proposal

Overview of FPGA (Khuyen Nguyen):


Programmable Logic Device(PLD) was once a popular choice among hardware designers due to its low NRE cost and readily available IC. However, this old class technology is getting pushed aside, paving way for the field programmable gate array(FPGA). FPGA consists of configurable logic blocks( through software), programmable I/O blocks, and programmable interconnects. FPGAs offer more general connectivity among logic blocks, which in turn allow a more complex design. Designers can mold the FPGA, by programming it, into desire functionalities.

Current technology allows FPGA to be used with either SRAM,Antifuse, or Flash. SRAM allows reprogram abililty and fast speed. However, it is volatile and you have to program every it powers up. It has low IP security due to the external file configuration. Plus, SRAM requires high power consumption. Antifuse technology is almost the opposite. It can only be programmed once, but provide good IP security do to internal configuration and low power consumption. Flash technology is a compromise between the two. It is reprogrammable, nonvolatile, good security, and medium power consumption.

Project Design and Layout (Khuyen Nguyen):


Since we are working in a group of four. It is most likely that we are going to implement this FPGA simulator in both VHDL and C++. Of course, we will integrate our C++ code into SimpleScalar as specified by the professor.
Before we decided on this project we did a thorough tradeoff analysis of each project possibilities.
As it stands, we have decided to work on the FPGA instead. Please bear with the out of the boundary analyzation in our previous tradeoff.

Tradeoffs-Xilinx XS40 vs. Triscend E5(Dennis You):

VHDL(Dennis You):

C++ Simulator(Roberto Hernandez):


The C++ simulator will be a little bit more challenging than the VHDL simulator. This is because the many gates that are already built into VHDL are not part of any C++ library. In short, we will be building the whole system from the ground up. Fortunately, C++ has a very good object oriented system. I believe that if we view each element as an object, the complexity of the project will be diminished.
Another issue that must be addressed, is that C++ is a sequential language, running a process from top down. VHDL does not do this. So the behaviour might change for a C++ created object to that of VHDL one.

Time of completion(Dennis You):

Project Cost(Dennis You):

Implementation(Dennis You):

Project Complexity (Manuel Minwary):


For the most part, each individual component of FPGA will be prety straight forward to implement. The CLB is nothing more than a few LUTs, MUXs, and a Flip Flops arranged in a certain way.

We all have learn how to design a MUX and Flip Flop. LUT is something new but it is simply a type of memory similar to a register, which we also have learn how to design.

The I/O cell is also a straight forward design to implement. It also consist of MUXs, Flip Flops, and other components that we have learn how to design in previous class.

The exception to this is the Switch Matrix. At this present time of writing the proposal, we have not figure out how to design the Switch Matrix. Is not that the component is overly complex, its just that while we know how it works, designing and implementing it we are still at a lost. We shall have to implement this component later after further research to understand how to exactly design it. So perhaps while we are designing the CLB and I/O cell, we will research Switch Matrix at same time. When we are done designing the CLB and I/O we will have enough understanding of Switch Matrix to be able to design it.

Another roadblock of complexity that I see designing the FPGA is when we are done with designing each individual component, we will have to connect these individual components together. While we still do not know how many CLB FPGA that we are supposed to be designing, even a 10x10 CLB design will be very time consuming to connect together. Plus it will be very suceptable to human error, it is very easy for a small connection error to totaly mess up the FPGA design. And once there is an error it will be hard to track down the error to that single connection when there are so many connections present in FPGA.

It would be better for us to work maybe slower but more accurate, or just connect a small FPGA first, perhaps only 4x4, then grow it from there to the specified size.

Last complexity that we are worried about is the timing issue, with many component connected together it will be very hard to keep track of the correct timing.

Team Division(Roberto Hernandez):


While it might be easier to do the project in teams of two, most real projects incorporate the use of large groups. It is for this reason that we are working with a team of four. The reasoning behind this decision is that this class is meant to prepare us for the actual type of work that we will be facing in today's industry. As the projects become greater in size and complexity, it is increasingly more difficult to find small groups and almost impossible to find "lone wolf" developers.

It is, therefore, seriously important to learn the skills necessary to operate as the member of a team and learn to work in a team environment. For this reason we will be employing a technique known as extreme programming. In this technique, two people sit down in one terminal to write one program. Also, programs are writen in small iterations which are tested exhaustively to insure their correctness. We believe that this fits this project perfectly since one of the conditions is that everyone knows what is going on (team programming) and that there is a quick time to first prototype(small iterations).

Configurable Logic Device: I/O blocks & Interconnection:

List of Parts: