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The already complex task of synergistic design of compilers and architectures has become even more challenging due to two major factors. First a wide range of applications, including media, network, and cognitive information processing, have emerged whose performance is characterized by multiple and varying optimization criteria. Second a wide range of computing devices have been introduced that vary greatly in memory, processing, communication, and energy resources. To address the above complexity there is a great need for systematically automating the tasks of analyzing and characterizing application behavior, identifying performance bottlenecks, and searching for solutions that exploit program behavior for addressing performance bottlenecks.
In this talk I will describe a novel program representation that lays the foundation for a framework that will address the above challenges. The Whole Execution Trace (WET) combines the dynamic profile data (including control flow, value, address, and dependence profiles) that is collected from a program run with the static program representation. The WET design leads to a compact and easily traversable representation. Our experiments project that a WET resulting from execution of 2 Billion statements can be stored in 1 Gigabyte of storage. As an application of WET I will describe the first practical dynamic slicing algorithm. Since its introduction over 15 years ago, numerous applications of dynamic slicing aimed at improving software quality, reliability, security, and performance have been identified. However, no practical algorithm for dynamic slicing has been developed. Most existing algorithms run out of memory for realistic program runs. The only existing algorithm that overcomes the memory problem takes several minutes to compute slices while the WET based algorithm takes only few seconds to compute the same slices. As the next step in our research we will pursue techniques for mining WET to identify program characteristics that can be exploited for alleviating performance bottlenecks.